Passivated tiered gate structure transistor and fabrication...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate

Reexamination Certificate

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Details

C438S574000, C438S579000, C257SE21205

Reexamination Certificate

active

07608497

ABSTRACT:
A method for fabricating a tiered structure includes forming a gate on a semiconductor substrate. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening through it to define the gate foot over the substrate. After forming the gate foot, the gate foot mask is stripped and a passivation layer is formed over the gate foot and the substrate. A gate head mask is formed over the gate foot with the gate head mask exposing a portion of the passivation layer on a top portion of the gate foot. The portion of the passivation layer on the top portion of the gate foot is removed to expose the top portion of the gate foot. A gate head is formed on the top portion of the gate foot using the gate head mask. A lift-off process is performed, removing the gate head mask.

REFERENCES:
patent: 5053348 (1991-10-01), Mishra et al.
patent: 5500381 (1996-03-01), Yoshida et al.
patent: 5693548 (1997-12-01), Lee et al.
patent: 5770525 (1998-06-01), Kamiyama
patent: 5981319 (1999-11-01), Lothian et al.
patent: 6051454 (2000-04-01), Anda et al.
patent: 6204102 (2001-03-01), Yoon et al.
patent: 6294446 (2001-09-01), Ishikawa
patent: 6387783 (2002-05-01), Furukawa et al.
patent: 6417084 (2002-07-01), Singh et al.
patent: 6737202 (2004-05-01), Gehoski et al.
patent: 7041541 (2006-05-01), Behammer
patent: 7387955 (2008-06-01), Ahn et al.
patent: 7439166 (2008-10-01), Milosavljevic et al.
patent: 2003/0119233 (2003-06-01), Koganei
patent: 2004/0063303 (2004-04-01), Behammer
patent: 2004/0082158 (2004-04-01), Whelan et al.
patent: 2007/0134862 (2007-06-01), Lim et al.
R. Grundbacher, I. Adesida, Y.-C. Kao, A.A. Ketterson, Single step lithography for double-recessed gate pseudomorphic electron mobility transistors, J. Vac. Sci. Technol. B 15 (1), pp. 49-52, American Vacuum Society, Jan./Feb. 1997.
USPTO Notice of Allowance and Fees Due, mailed Jan. 14, 2009 for U.S. Appl. No. 11/517,791, filed Sep. 8, 2006, Inventor Milosavljevic.
USPTO Office Action (OA) mailed Nov. 29, 2007 for U.S. Appl. No. 11/150,439, filed Jun. 11, 2005, inventor Milosavljevic.

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