Partial silicidation method to form shallow source/drain junctio

Details Partial silicidation method to form shallow source/drain junctio Partial silicidation method to form shallow source/drain junctio

1998-02-13

2000-06-06

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438655, H01L 21336, H01L 2144

Patent

active

060717823

ABSTRACT:
A process of forming silicide at uniform rates across the entire source/drain region is provided. A two-step annealing method permits the thickness of the silicide formed on the edge of a silicon electrode to be substantially the same as it is in the center of the electrode. A first, low temperature anneal begins the salicidation process across the source/drain electrode surface. The time and temperature are controlled so that the metal is only partially consumed. The annealing is interrupted to remove excess silicidation metal, especially the unreacted metal overlying oxide areas neighboring the silicon electrode. Then, the silicidation is completed at a higher temperature anneal. Because the excess metal has been removed, the resulting silicide layer is uniformly flat, permitting the transistor to be fabricated with shallow junction areas and low leakage currents. In one embodiment of the invention, the crystalline structure of source and drain surfaces is annihilated before the deposition of metal, to lower annealing temperatures and add precise control to the silicidation process. A transistor having a uniformly thick silicide layer, fabricated in accordance with the above-mentioned method, is also provided.

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