Parallel and series-coupled transistors having gate...

Details Parallel and series-coupled transistors having gate... Parallel and series-coupled transistors having gate...

1998-09-25

2002-05-07

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S596000, C438S947000

Reexamination Certificate

active

06383872

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to transistors coupled in series and/or in parallel to form a logic gate and, more particularly, to a more accurate method for forming ultra-small gate conductors for each of the transistors.
2. Description of the Related Art
Fabrication of a metal-oxide semiconductor (“MOS”) transistor is well known. The manufacture of an MOS transistor begins by defining active areas where the transistor will be formed. The active areas are isolated from other areas on the semiconductor substrate by various isolation structures formed upon and within the substrate. Isolation structures come in many forms. For example, the isolation structures can be formed by etching trenches into the substrate and then filling the trenches with a dielectric fill material. Isolation structures may also be formed by locally oxidizing the silicon substrate using the well recognized LOCOS technique.
Once the isolation structures are defined between transistor active areas, a gate dielectric is formed. Typically, the gate dielectric is formed by thermal oxidation of the silicon substrate. Thermal oxidation is achieved by subjecting the substrate to an oxygen-bearing, heated ambient in, for example, an oxidation furnace or a rapid thermal annealer (“RTA”). A gate conductor material is then deposited across the entire dielectric-overed substrate. The gate conductor material is preferably polycrystalline silicon, or polysilicon. The polysilicon layer is then patterned using a photolithography mask. The mask allows select removal of a light-sensitive material deposited entirely across the polysilicon. The material which is exposed can, according to one embodiment, be polymerized, and that which is not exposed removed. Selective polymerization is often referred to as the “develop” stage of lithography. The regions which are non-polymerized are removed using the etch stage of lithography.
A typical n-channel MOS (“NMOS”) transistor employs n-type dopants placed into a p-type substrate. Conversely, a typical p-channel MOS (“PMOS”) transistor comprises p-type dopants placed into an n-type substrate. The substrate is generally a single crystalline silicon structure. Regions of the substrate which receive dopants on opposite sides of the gate conductor are generally referred to as junction regions, and the distance between junction regions is typically referred to as the physical channel length. After implantation and subsequent diffusion of the junction regions, the distance between the junction regions becomes less than the physical channel length and is often referred to as the effective channel length (“Leff”). In high density designs, not only does the physical channel length become small, so too must the Leff. As Leff decreases below approximately 1.0 &mgr;m, for example, a problem known as short channel effects (“SCE”) becomes predominant.
Integrated circuits designed with relatively small physical channel lengths in densely patterned circuit areas require careful attention be directed to the mechanism by which the gate conductor is formed. For example, if a set of gate conductors within a densely patterned area become too small, then SCE will be predominant for those transistors. It might be that the small Leff transistors will prematurely turn on or will incur sub-threshold currents, more so than the other transistors—even though all transistors were designed to have the same physical channel length.
Slight variations in gate conductor length (i.e., physical channel length) even though not intentional may drastically alter the performance of a circuit design with relatively small physical channel lengths. This problem is significant in areas of densely patterned gate conductors such as, for example, logic areas containing numerous interconnected NAND and NOR gates. While it is desired that the series-connected and parallel-connected transistors within each logic gate be closely spaced to one another, it is equally desired that those transistors maintain a consistent channel length amongst themselves. If, for example, Leff of one parallel-connected transistor differs from that of the other parallel-connected transistor, then uneven turn-on transience may occur across the parallel connection.
The conventional lithography used to pattern closely spaced gate conductors (e.g., gate conductors of series-connected and parallel-connected transistors) suffers many drawbacks. For example, selective exposure is highly dependent upon accurately placing light on the light-sensitive material. Furthermore, light-sensitive material must consistently respond to the light with fine-line resolution. Any elevational disparity on which the polysilicon resides will result in slight changes in the point at which the light impinges on the light-sensitive material. This results in a variation in the polymerized
on-polymerized boundary.
It is therefore desirable to produce gate conductors which have an extremely small physical channel length to achieve high density logic cells. Although small in physical channel length, the desired gate conductors must be of consistent size across a somewhat elevationally disparate topography. In order to accurately produce a small gate conductor, a process must be used which avoids lithographic limitations of exposure, develop and etch cycles used in defining conventional gate conductors upon a gate dielectric. In order for a transistor which employs a relatively small gate conductor to achieve commercial success, improvements must be undertaken not only to the lithography procedure but also possibly to the junction itself. It may be necessary to incorporate a lightly doped drain (“LDD”) region at the interface between the junction and the channel area underlying the gate conductor. As Leff decreases commensurate with gate conductor size, LDD implants must be carefully controlled so as not to encroach into the relatively short channel while at the same time source/drain implants formed within the junctions must be sufficiently concentrated to minimize hot carrier effects (“HCF”).
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an improved transistor configuration hereof. The improved transistor can be either a p-channel or an n-channel transistor. Importantly, p-channel transistors can be incorporated with n-channel transistors to form a logic gate. The logic gate comprises series-connected and parallel-connected transistors closely spaced and connected to form, for example, one or more NAND gates or NOR logic gates.
In regions where logic gates are prevalent, closely spaced transistors are needed having relatively short physical channel lengths. To define an ultra short physical channel length which maintains its effective consistency for each transistor across one or more logic gates, the gate conductors of those transistors are beneficially formed outside the conventional lithography process. Instead of depositing a gate conductor material across an entire planar surface, the present process employs a gate conductor material formed so that it is bounded on one lateral surface against a sacrificial structure. The bounded gate conductor can be formed by depositing a layer of polysilicon across and adjacent to the sacrificial structure. The gate conductor layer is then partially removed using an anisotropic etch technique, leaving a gate conductor which abuts the sacrificial structure. The height of the sacrificial material and the deposition thickness of the gate conductor material will define the entire gate conductor geometry.
According to one embodiment, spacers can be formed on opposed lateral surfaces of the gate conductor. The spacer on one lateral surface can be of dissimilar thickness than the spacer on the opposing lateral surface. Of benefit is the asymmetrical design of the ensuing transistor, wherein the drain-side spacer can be made thicker than the source-side spacer. Since the spacers define source/drain implant alignment, dissimilar spacer thicknesses will cause the drain impla

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