Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2002-04-26
2003-12-02
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S165000, C438S278000
Reexamination Certificate
active
06656778
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor fabrication and, more particularly, to a passivation structure for, e.g., flash memory, and a method for fabricating such passivation structure.
In the fabrication of semiconductor devices, passivation layers are used to protect the underlying device components from moisture, contamination, deterioration of electronic properties, and physical damage. The passivation layers are typically formed of silicon nitride or silicon dioxide. These materials prevent mobile ions from entering the device structures and causing problems such as threshold voltage shifting.
In some devices, multiple layer passivation structures are used to relieve stress in the underlying metal and dielectric layers. One known five-layer passivation structure includes a PEOX layer, a high ultraviolet transmittance silicon nitride layer, a spin-on glass (SOG) layer, a layer of silicon oxynitride having a thickness of 6,000 angstroms, and a layer of PSG having a thickness of 9,000 angstroms. One drawback of this structure is that the fabrication process used to form this structure is complicated, time consuming, and expensive. Another drawback of this structure is that the PSG layer, which is formed by plasma enhanced chemical vapor deposition (PECVD), has a granular structure and therefore does not effectively prevent mobile ions from penetrating the PEOX layer.
U.S. Pat. No. 6,261,944 to Mehta et al. discloses a four-layer passivation structure composed of a first PECVD oxide layer, a SOG layer, a second PECVD oxide layer, and a PECVD silicon nitride layer. This passivation structure suffers from the drawbacks that it is complicated and relatively expensive to fabricate and has bad erase characteristics.
U.S. Pat. No. 5,549,786 to Jones et al. discloses a dielectric-SOG-dielectric passivation structure that is composed of a first PECVD silicon nitride layer, a SOG layer, and a second PECVD silicon nitride layer. Unfortunately, this passivation structure does not effectively prevent the underlying device components from moisture, mobile ions, and physical damage.
U.S. Pat. No. 5,483,097 to Ohtsuki et al. discloses a device protecting layer composed of an ultraviolet transmissible silicon nitride film. This silicon nitride film, which is formed by a PECVD process, is relatively thick and therefore induces a large amount of stress. This is undesirable because the induced stress may damage the top metal in a semiconductor device.
In view of the foregoing, there is a need for a passivation structure that not only protects the underlying device components effectively, but also can be fabricated using a method that is quicker and less expensive than conventional methods for forming passivation structures.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills this need by providing an effective passivation structure that includes a minimum number of layers. A method for forming this passivation structure also is described.
In accordance with one aspect of the present invention, a passivation structure for a semiconductor device is provided. In this passivation structure, a high ultraviolet transmittance silicon nitride (UV-SiN) layer substantially conformally overlies a plurality of top metal lines, which are formed over a semiconductor substrate, such that portions of a top surface of the UV-SiN layer define a plurality of topographical hollows between adjacent top metal lines. A spin-on glass (SOG) material overlies the portions of the UV-SiN layer that define the plurality of topographical hollows. A silicon oxynitride (SiON) layer overlies the UV-SiN layer and the SOG material.
In one embodiment, the UV-SiN layer has a thickness of about 4,000 angstroms. In one embodiment, the SOG material is a silicate-based material or a siloxane-based material and has a thickness of about 3,400 angstroms. In one embodiment, the SiON layer has a thickness in a range from about 8,000 angstroms to about 10,000 angstroms. In one embodiment, the semiconductor device is a flash memory.
In accordance with another aspect of the present invention, a method for forming a passivation structure for a semiconductor device is provided. In this method, a substrate having a plurality of top metal lines formed thereover is provided. A substantially conformal layer of UV-SiN is formed over the substrate such that portions of a top surface of the UV-SiN layer define a plurality of topographical hollows between adjacent top metal lines. The plurality of topographical hollows is at least partially filled with a SOG material. A layer of SiON is formed over the UV-SiN layer and the SOG material.
The passivation structure of the present invention advantageously provides an enhanced passivation effect using a minimum number of layers. The relatively thick SiON layer not only protects the underlying features from moisture, but also prevents alkali metal ions from penetrating therethrough. In addition, the SiON layer protects the SOG material during subsequent wet etching processes. By virtue of user fewer layers than are used in conventional passivation structures, the method for forming a passivation structure of the present invention is shorter and less expensive than the methods used to form conventional passivation structures.
It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 5714408 (1998-02-01), Ichikawa et al.
patent: 6038171 (2000-03-01), McElheny
patent: 6137156 (2000-10-01), Ichikawa et al.
patent: 6274900 (2001-08-01), San et al.
patent: 6383870 (2002-05-01), San et al.
patent: 6551867 (2003-04-01), Ozeki et al.
Chen I-Yueh
Chen Jung-Chieh
Lee Tung-Ta
Lu Chen-Chien
Jr. Carl Whitehead
Macronix International Co. Ltd.
Schillinger Laura M
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