Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-06-12
2002-04-30
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S148000, C438S155000, C438S161000
Reexamination Certificate
active
06380006
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a pattern formation method for a semiconductor device such as a thin film transistor and a method of manufacturing a display using the pattern formation method, particularly relates to a pattern formation method using technique for reflowing resist and a method of manufacturing a thin film transistor for a display using the pattern formation method.
2. Description of the Prior Art
The advanced integration of a semiconductor device has been achieved by photolithography which is a means for forming a minute pattern and dry etching technique. However, when the performance of a semiconductor device is enhanced as described above, the manufacturing process is advanced and the manufacturing cost is increased.
Then recently, it is demanded to integrate pattern manufacturing processes and to reduce the number of total processes by (1) tapering a wiring pattern which is one of means for making the contents of a process satisfactory and (2) greatly reducing the manufacturing cost of a semiconductor device.
A case that normal wiring is formed instead of tapered wiring (hereinafter called a first conventional example) and a case that wiring in a well-known example is formed (hereinafter called a second conventional example) out of prior art will be described referring to drawings below.
FIGS. 25A
to
25
D are schematic sectional views showing wiring pattern for explaining the first conventional example n the order of the manufacturing processes.
As shown in
FIG.25A
, a metallic film
402
made of an aluminum alloy and others is formed on base material
401
such as a glass substrate. The thickness of the metallic film
402
is approximately 1 &mgr;m. A resist mask
407
is formed in a predetermined region on the metallic film
402
by well-known photolithography.
Next, as shown in
FIG. 25B
, the resist mask
407
functions as a mask for etching, first etching is applied to the metallic film
402
and a first tapered layer
415
is formed.
Next, as shown in
FIG. 25C
, the resist mask
407
reflows by heating the whole at 150 to 200° C. and hangs sideways to be a thermally reflowed resist mask
413
.
Next, as shown in
FIG. 25D
, second etching is applied to the residual metallic film
402
using the thermally reflowed resist mask
413
as an etching mask and wiring
411
having a second tapered layer
416
in the lower part is formed.
FIGS. 26A
to
26
C are schematic sectional views showing the manufacturing method of the second conventional example (Japanese published unexamined patent application No. 2000-133636) in the order of manufacturing processes.
As shown in
FIG. 26A
, a metallic film
422
made of an aluminum alloy and others is formed on base material
421
. The thickness of the metallic film
422
is approximately 1 &mgr;m. A resist mask
427
is formed in a predetermined region on the metallic film
422
by well-known photolithography.
Next, as shown in
FIG. 26B
, the resist mask
427
functions s a mask for etching, first etching is applied to the metallic film
422
and a first tapered layer
435
is formed.
Next, after the first tapered layer
435
shown in
FIG. 26B
formed, the resist mask
427
is dipped in organic silane solution which is a sililation reagent together with the base material
421
. Or the resist mask
427
is exposed to the vapor of organic silane. As described above, the resist mask
427
is sililated.
The resist mask
427
swells by the sililation and as shown in
FIG. 26C
, the swollen sililated resist mask
433
is formed. The pattern width of the sililated resist mask
433
swollen by the sililation is increased than the pattern width of the resist mask
427
shown by a broken line. For the sililation reagent, silazane and others are used.
Next, second etching is applied to the residual metallic film
422
using the swollen sililated resist mask
433
as an etching mask and wiring
431
having a second tapered layer
436
in the lower part is formed. However, as the adhesion strength of the swollen sililated resist mask
433
is weak, the first tapered layer
435
is etched from the side and a side-etched part
432
in a crooked shape may be formed in the first tapered layer
435
. As a result, the wiring
431
is formed.
A present case of the formation of wiring for which the reduction of the number of manufacturing processes is demanded (hereinafter called a third conventional example) and a case of the formation of wiring in which the number of the manufacturing processes is reduced according to the demand (hereinafter called a fourth conventional example) out of the prior art will be described referring to drawings below.
FIGS. 27A
to
27
C are schematic sectional views showing the manufacturing process of a part of reverse staggered-type TFT for explaining the third conventional example.
As shown in
FIG. 27A
, a gate electrode
442
is formed on base material
441
formed by a transparent substrate made of glass and others, a gate insulating film
443
, an amorphous silicon (a-Si) film
444
, an N+-type amorphous silicon (N+-type a-Si) film
455
and a metallic film
446
are laminated and further, first resist masks
447
and
448
are formed on the metallic film
446
by well-known photolithography.
Next, as shown in
FIG. 27B
, the metallic film
446
and the N+-type a-Si film
445
are dry-etched using these first resist masks
447
and
448
as an etching mask.
As a result, a source electrode
451
, an ohmic contact layer for the source electrode
449
, a drain electrode
452
and an ohmic contact layer for the drain electrode
450
are formed. Afterward, the resist masks
447
and
448
first formed are peeled and removed.
Next, as shown in
FIG. 27C
, the source electrode
451
, the ohmic contact layer
449
, the drain electrode
452
and the ohmic contact layer
450
are coated, a part of the surface of the a-Si film
444
is coated and a second resist mask
453
is formed by well-known photolithography.
Next, the a-Si film
444
is etched using the second resist mask
453
as an etching mask and an island layer
454
is formed. The second resist mask
453
is peeled and removed.
As a result, reverse staggered-type TFT is formed. The description of the succeeding processes is omitted, however, for example, a pixel electrode, a passivation insulating film and others are formed and an active matrix TFT-LCD device is formed.
FIGS. 28A
to
28
C are schematic sectional views showing the manufacturing process of a part of reverse staggered-type TFT for explaining the fourth conventional example disclosed in Japanese published unexamined patent application No. 2000-133636.
FIG. 28A
is similar to
FIGS. 27A and 27B
related to the third conventional example.
Next, resist masks
467
and
468
are dipped in the solution of organic silane. Or they are exposed to the vapor of organic silane. As a result, the resist masks
467
and
468
are sililated. The resist masks
467
and
468
are swollen by the sililation and as shown in
FIG. 28B
, they are united to be one swollen sililated resist mask
473
. In the swelling in this case, the dimension of the resist masks
467
and
468
respectively shown by a broken line is respectively swollen by the volume of 0.1 to 2.0 &mgr;m
Next, second etching is applied using the swollen sililated resist mask
473
as an etching mask and an a-Si film
464
is etched.
As a result, as shown in
FIG. 28C
, an island layer
471
is formed. Afterward, the swollen sililated resist mask
473
is peeled and removed.
As a result, reverse staggered-type TFT is formed. The description of the succeeding processes is omitted, however, for example, a pixel electrode, a passivation insulating film and others are formed and active matrix TFT-LCD device is formed.
FIGS. 29A
to
29
C are schematic sectional views showing the manufacturing process of a part of reverse staggered-type TFT for explaining a fifth conventional example disclosed in Japanese published unexamined patent application No. 2000-131719.
FIG. 29A
Lebentritt Michael S.
Luhrs Michael K.
Young & Thompson
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