Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-10-12
2003-09-02
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S153000, C438S155000, C438S239000, C438S241000
Reexamination Certificate
active
06613615
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits and, more particularly, to forming body contacts to a surface layer of a silicon-on-insulator integrated circuit chip.
2. Background Description
Dynamic Random Access Memory (DRAM) chips are well known. A DRAM cell is essentially a capacitor for storing charge and a pass transistor (also called a pass gate or access transistor) for transferring charge to and from the capacitor. Data (1 bit) stored in the cell is determined by the absence or presence of charge on the storage capacitor. Because cell size determines chip density, size and cost, reducing cell area is one of the DRAM designer's primary goals. Reducing cell area is done, normally, by reducing feature size to shrink the cell. Unfortunately, shrinking cell size reduces storage capacitance and, correspondingly, the charge stored in each cell.
Each cell is read by coupling the cell's storage capacitor (through the access transistor) to a bitline, which is a larger capacitance, and measuring the resulting voltage difference on the bit line. Reducing the storable charge reduces the voltage difference. Typically, the bit line signal is a few hundred millivolts (mv) that develops asymptotically from the time that the access transistor is turned on. To achieve high performance, state of the art sense amplifiers, typically a pair of cross coupled transistors, must sense a potential difference that is something less than the ultimate few hundred millivolt signal. The smaller the potential difference that the sense amplifier can sense the better. So, any difference in the transistors in the cross coupled pair increases the sensable potential difference and, therefore, slows sensing. Consequently, it is important that the transistors in the cross-coupled pair, which are normally field effect transistors (FETs), have identical device characteristics and are what is known as a balanced or matched pair.
In designing a balanced pair, great care is taken to insure that each transistor is influenced by ambient conditions identically with the other of the pair. However, other constraints may further complicate the task of designing a matched pair of transistors. For example, each sense amplifier may be constrained to fit on the same pitch as a pair of adjacent bit lines, each pair of adjacent bit lines being coupled to a corresponding sense amplifier. In this instance in addition to other constraints, the cross coupled transistor pair must fit in a very narrow pitch. This narrow pitch further complicates transistor design placement (layout) to achieve a balanced pair, especially for silicon-on-insulator circuits.
SOI transistors may be formed on the surface of a silicon layer isolated from a silicon substrate by a buried oxide (BOX) layer. In a typically complex series of mask steps, shallow trenches filled with oxide isolate SOI islands of the surface silicon layer on which circuits are formed. Local contacts are made to each of the circuit's conduction wells and at least one body contact is made to the silicon layer island. For most circuits it is sufficient to form a single body contact to a p-type silicon island layer at a common point with n-type FETs (NFETs) distributed around the island. Normally, slight variations in device characteristics such as device thresholds, are negligible, neglectable and not given much consideration for typical logic circuits such as decoders or timing logic.
However, these otherwise slight threshold variations can seriously handicap an otherwise well designed sense amplifier layout, unbalancing a matched pair. This is especially a problem for a SOI sense amplifier where asymmetric body charging can exacerbate device differences. Further, to overcome these variations by providing individual body contacts to each pair of sense amplifier FETs can increase sense amplifier area and, still may not result in a matched pair of transistors. See for example, J. A. Mandelman et al., “SOI MOSFET Mismatch Due To Floating Body Effects,” Proceedings 1997 IEEE International SOI Conf., October, 1997, pp. 164-5. In addition each added mask step increase chip turnaround time, increases chip processing complexity and chip cost.
Thus, there is a need for SOI layer body contacts that can be formed at adjacent pairs of closely spaced transistors without increasing the layout area of the transistors, adding mask steps and processing complexity.
SUMMARY OF THE INVENTION
It is therefore a purpose of the present invention to improve the Dynamic Random Access Memory (DRAM) performance;
It is another purpose of the present invention to increase DRAM sense amplifier signal margin;
It is yet another purpose of the present invention to increase DRAM sense amplifier signal margin without increasing sense amplifier area;
It is yet another purpose of the present invention to increase DRAM sense amplifier signal margin without increasing the number of mask steps required to form the DRAM;
It is yet another purpose of the present invention to improve threshold matching for matched transistor pairs;
It is yet another purpose of the present invention to form matched transistor pairs;
It is yet another purpose of the invention to form individual body contacts at each pair of matched transistors without increasing the area of the matched transistor pairs.
The present invention is a method of forming a silicon on insulator (SOI) body contact at a pair of field effect transistors (FETs), a sense amplifier including a balanced pair of such FETs and a RAM including the sense amplifiers. A pair of gates are formed on a SOI silicon surface layer. A dielectric bridge is formed between a pair of gates when sidewall spacers are formed along the gates. Source/drain (S/D) conduction regions are formed in the SOI surface layer adjacent the sidewalls at the pair of gates. The dielectric bridge blocks selectively formation of S/D conduction regions. A passivation layer is formed over the pair of gates and the dielectric bridge and a contact mask is formed on the passivation layer. Contacts are opened partially through the passivation layer. Then, a body contact is opened through the bridge to SOI surface layer and a body contact diffusion is formed. Using the same contact mask, contact openings are completed through the passivation layer at the S/D diffusions. Tungsten studs are formed in the contact openings. The balanced transistors may be cross coupled and used as a sense amplifier in a RAM.
REFERENCES:
patent: 5895239 (1999-04-01), Jeng et al.
patent: 6312994 (2001-11-01), Nakamura
Assaderaghi Fariborz
Hargrove Michael J.
Mandelman Jack A.
Rohrer Norman J.
Smeys Peter
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