Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1994-10-06
1997-04-22
Yoo, Do Hyun
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
3651851, 438265, 438594, G11C 1300
Patent
active
056228813
ABSTRACT:
Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.
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patent: 5402372 (1995-03-01), Bergemont
"A New Self-Aligned Planar Array Cell for Ultra High Density EPROMS"; A. T. Mitchell et al.; Texas Instruments Incorporation; IEEE 1987; pp. 548-551.
Acocella Joyce E.
Galli Carol
Hsu Louis Lu-Chen
Ogura Seiki
Rovedo Nivo
International Business Machines - Corporation
Petraske Eric W.
Yoo Do Hyun
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