Parasitic surface transfer transistor cell (PASTT cell) for...

Details Parasitic surface transfer transistor cell (PASTT cell) for... Parasitic surface transfer transistor cell (PASTT cell) for...

2001-05-17

2002-08-06

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000

Reexamination Certificate

active

06429081

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to Flash memory cell devices, and more particularly, to a parasitic surface transfer transistor (PASTT) Flash memory cell for bi-level and multi-level NAND Flash memory structures and a method of manufacture thereof.
(2) Description of the Prior Art
As the blooming market of multi-media expands, high-density Flash memories are being applied to mass storage applications such as handy terminals, solid state cameras, and PC cards. Flash memories have many advantages, such as, fast access time, low power dissipation, and robustness. However, in order to gain greater market access, several requirements must be satisfied. First, the bit cost must be made lower. Bit cost is estimated at about $1.00 per megabyte by the 2000. Second, Flash memories must have high reliability. The target reliability, which is related to program/erase endurance and data retention, is a ten-year data retention time after one million program/erase cycles. Finally, high speed programmability, on the order of one microsecond per byte, and single 2.5 to 3.3 Volt power supply operation are emerging requirements.
Referring now to
FIG. 1
, a prior art EEPROM structure is illustrated. This Flash memory structure is a NAND configuration. A NAND configured EEPROM allows the individual cell size to be reduced without scaling the design or layout rules. The number of bit line contacts is reduced by connecting each Flash cell in series. In addition, such a prior art NAND-structure EEPROM would use a bi-polarity, Fowler-Nordheim tunneling program/erase method to achieve high reliability and high-speed programming.
In the example NAND structure, four Flash memory cells
46
,
50
,
54
, and
58
are connected in series between the bit line
10
selection transistor, SLG
1
42
, and the source
14
selection transistor, SLG
2
62
. In the case of a bi-level memory system, the state of each cell in the array is either “0” or “1”. To determine the particular state of an individual cell, the cell must be selected and tested. In the example case, the contents of the Flash cell
50
are read. To read the cell
50
, the gate of the bit line selection transistor, SLG
1
42
, is biased to 5V and turned ON. The source selection transistor, SLG
2
62
, is likewise turned ON. The non-selected word lines, WORDLINE
1
22
, WORDLINE
3
30
, and WORDLINE
4
34
are all biased to 5V and, therefore, turned ON. WORDLINE
2
26
is then biased to a reading voltage, which is a voltage between the “1” state threshold voltage (V
th
) and the “0” state threshold voltage. For example, if the “0” state (erased) threshold voltage of the Flash cell is −1 Volt and the “1” state (programmed) threshold voltage of the Flash cell is 2 Volts, then the reading voltage may be 0.5 Volts. If WORDLINE
2
26
is biased to 0.5 Volts, then cell
50
will only conduct if it is in the “0” state. The cell
50
will not conduct if it is in the “1” state. Current flow or voltage discharge on the BITLINE-
1
10
node can detect the state of the cell
50
based on this setup.
Referring now to
FIG. 2
, a graphical representation of the bi-level performance of the prior art NAND Flash structure is shown. The V
th
distribution of the bi-level programming scheme is illustrated. The “0” level state is defined as the erased state of a cell in which the V
th
level is controlled only by the inherent properties of the cell transistor without any floating gate charge storage. In this example, the Flash cells in the memory device exhibit a distribution
70
of “0” level voltage thresholds of between about −0.5 Volts and −3 Volts.
The “1” level state is defined as the programmed state for a cell in which the V
th
value is modified by the presence of negative charge on the floating gate. In this example, the Flash cells in the memory device exhibit a distribution
74
of “1” level voltage thresholds of between about 0.5 Volts and 3.5 Volts covering a range R
21
. As described above, during a reading operation, the unselected cells in the bit-line series of the cell being read must be turn ON. The unselected cells must be driven with a gate voltage
78
that is greater than the highest “1” level voltage threshold so that all the unselected cells are guaranteed to be in the ON state during a read. Note that a wide “1” level range R
21
is desirable for insuring easy and fast programming of the cell. However, a wide range makes it difficult to insure that all unselected cells will be ON during reads to the selected cell. It is desirable to maintain a wide R
21
value while providing a maximum separation of the “1” level distribution
74
and the unselected gate voltage distribution
78
.
It has been found that the cost per bit of Flash memory devices can be significantly reduced through the use of multi-level schemes in which more than two levels are encoded onto the threshold voltages of the cells. For example, a four-level scheme, wherein “0”, “1”, “2”, and “3” are encoded into a sequence of escalating threshold voltage values, has been shown to reduce the required area for a fixed memory size by about 60%. In such a system, the programming technique allows the amount of floating gate charging to be controlled such that discrete V
th
values are attained for each level state. The “0” state remains the erased or inherent V
th
state.
Referring now to
FIG. 3
, the V
th
distribution for a four-level NAND EEPROM scheme is illustrated. Again, the “0” level reflects the non-charged state of a cell and exhibits a fairly wide distribution
82
below 0 Volts. However, the “1” level distribution
86
must be much narrower than in the bi-level system so that the additional “2” and “3” levels can be included.
Note that the “1”, “2”, and “3” levels are narrowly distributed
86
,
90
, and
94
and have tight ranges of R
1
, R
2
, and R
3
, respectively. For example, each range R
1
, R
2
, and R
3
is about 0.6 Volts. Further, the levels are closely spaced with spacings S
1
and S
2
of about 0.8 Volts. Finally, the “3” level
94
must be spaced S
3
from the unselected gate voltage distribution
100
by about 0.6 Volts to insure correct operation. It is essential that the entire range of levels “1”, “2”, and “3” be encoded in less than about 4 Volts to insure proper operation during cell reads and, particularly, to insure that the unselected cell voltage of about 5 Volts will turn ON the highest “3” level cells. This very tight spacing and distribution scheme causes cell programming to be very slow. This is because the programmed cells must be verified within these tight level windows. In addition, data retention failures are greater because of these narrow level ranges.
To avoid the problems caused by the four-level scheme while achieving the advantage of smaller area, a side-wall transfer-transistor cell (SWATT) multi-level NAND Flash EEPROM has been developed. This technique provides low V
th
transistors in parallel with each Flash cell. These low V
th
transistors are guaranteed to turn ON at the unselected gate voltage regardless of the programmed state of their cell. This means that a wider voltage distribution can be designed for the “1”, “2”, and “3” levels. Programming speed and data retention are improved while achieving a small cell size of about 0.67 microns
2
for a 0.35 micron design rule. However, as will be seen in the following analyze, the SWATT Flash cell scheme has several disadvantages.
Referring now to
FIG. 4
, a cross-section of a partially completed SWATT Flash memory device is shown. At this stage of the processing sequence, a stack comprising a tunneling oxide layer
124
, a polysilicon layer
128
, and a cap oxide layer
132
has been deposited overlying the semiconductor substrate
120
. The stack
124
,
128
, and
132
has been patterned to define the floating gates for the Flash cells. Trenches
140
for shallow trench isolations (STI) have been etched into the semiconductor substrate
120
. Finally, a trench oxide filling layer
136
has been deposited.
Referring now to

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