Partial vertical memory cell and method of fabricating the same

Details Partial vertical memory cell and method of fabricating the same Partial vertical memory cell and method of fabricating the same

2006-04-25

2006-04-25

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S386000

Reexamination Certificate

active

07033886

ABSTRACT:
A partial vertical memory cell and fabrication method thereof. A semiconductor substrate is provided, in which two deep trenches having deep trench capacitors respectively are formed, and the deep trench capacitors are lower than a top surface of the semiconductor substrate. A portion of the semiconductor outside the deep trenches is removed to form a pillar between. The pillar is ion implanted to form an ion-doped area in the pillar corner acting as a S/D area. A gate dielectric layer and a conducting layer are conformally formed on the pillar sequentially. An isolation is formed in the semiconductor substrate beside the conducting layer. The conducting layer is defined to form a first gate and a second gate.

REFERENCES:
patent: 6514816 (2003-02-01), Lee

Affiliated with

Also associated with

Rating

Partial vertical memory cell and method of fabricating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Partial vertical memory cell and method of fabricating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Partial vertical memory cell and method of fabricating the same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3563729