Passivation of nitride spacer

Details Passivation of nitride spacer Passivation of nitride spacer

2001-08-02

2004-07-20

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S229000, C438S307000, C438S656000

Reexamination Certificate

active

06764912

ABSTRACT:

FIELD OF INVENTION
The invention pertains to passivating a silicon nitride spacer to prevent silicide bridging between the gate electrode and the source and drain regions.
BACKGROUND OF THE INVENTION
FIG. 1
shows a typical prior art MOSFET device
10
comprising a semiconductor substrate
11
, field oxide (FOX) regions
12
, source and drain regions
13
and
14
, and a gate electrode. The substrate
11
consists of a P-doped single crystalline silicon to form a P type substrate. The thick field oxide (FOX) regions
12
are formed on either side of the source and drain regions
13
and
14
for isolation purposes. The gate electrode is formed on the surface of semiconductor substrate between the source and drain regions. The gate electrode typically includes a thin silicon oxide layer
16
and a polysilicon layer
17
. Silicon dioxide spacers
18
formed on the sidewalls of the gate electrode. Refractory metal silicide contacts
19
and
20
are formed typically on the surface of drain and source regions
13
and
14
on the horizontal surface of substrate
11
and on the horizontal top surface
21
of the gate electrode by a process known as a self-aligned silicide or salicide process. The silicides result from the thermal reaction of the metal and silicon in regions
13
and
14
and polysilicon layer
17
.
While the sidewall spacers are intended to prevent bridging of the gate silicide region with either the source or drain silicide regions, as device geometries become smaller, bridging between the silicide formed on the top surface
21
and the metal silicide contacts
19
and
20
has again become a serious problem. It is known that native oxide or oxide residues from the anisotropic etching to form the silicon oxide spacers will form on the exposed top surface of the polysilicon gate as well as on the top surfaces of the source and drain regions. These oxides must be removed to allow the subsequent metal silicide formation to be successful because the oxides will prevent the reaction between the metal and the exposed silicon surfaces during the annealing step. In order to remove the oxides, the surfaces are typically treated with 1 vol. % HF solution prior to deposition of the metal. However, while hydrofluoric acid etches the native oxide, it also etches the silicon oxide spacers
18
causing significant thinning and exposing the surface of the polysilicon
17
in the gate structure resulting in a metal silicide being formed during the silicide process to cause bridging to occur on the sides of the polysilicon gate.
A solution to the problem is disclosed in U.S. Pat. Nos. 5,747,373 and 5,851,890 wherein a double insulator spacer is used to prevent the metal silicide bridging phenomena. Specifically, the spacer comprises two layers, a first layer comprising silicon oxide that is formed on the sides of the polysilicon gate and a second layer comprising silicon nitride which is formed on the first layer. The double layer prevents the oxide layer from being etched because it is not affected by the HF etchant.
However, the silicon nitride includes dangling silicon bonds that can react with the metal during the salicide process. Most notably this occurs with nickel. These bonds form a thin nickel silicide layer over the spacer. This thin layer leads to bridging between the gate electrode and the source and drain regions of the transistor which can result in an increase in transistor resistance.
It has been discovered that by coating the nitride layer with a thin layer of silicon oxide prior to the etching and the salicide process, the bridging problem is significantly reduced, if not eliminated.
SUMMARY OF THE INVENTION
The object of this invention is to provide passivate silicon nitride spacers by coating the spacers with a thin coating of silicon oxide to avoid silicidation bridging. To accomplish the object described above according to the present invention, there is provided a method for passivating a silicon nitride spacer which comprises the steps of covering the entire surface of a semiconductor substrate including source and drain regions, a gate electrode with a thin layer of silicon oxide, etching the top surface of the gate electrode and the top surfaces of the source and drain regions just prior to depositing the metal in the silicidation process. The other objects and characteristics of the present invention will become apparent from the further disclosure of the invention which is given hereinafter with reference to the accompanying drawing.


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