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Latch-up prevention for memory cells

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Lateral bipolar transistor with compensated well regions

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Lateral DMOS structure with lateral extension structure for...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Lateral DMOS transistor for RF/microwave applications

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Lateral doped channel

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Lateral double diffused MOS device and method for...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Lateral double-diffused metal oxide semiconductor (LDMOS)...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Lateral drain MOSFET with improved clamping voltage control

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Lateral heterojunction bipolar transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Lateral MOSFET having a barrier between the source/drain regions

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Lateral MOSFET having a barrier between the source/drain...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Lateral oxidation with high-K dielectric liner

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Lateral PNP and method of manufacture

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Lateral pocket implant charge trapping devices

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Lateral power semiconductor device for high frequency power...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Lateral trench MISFET and method of manufacturing the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Laterally diffused MOS transistor (LDMOS) and method of...

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Laterally double-diffused metal oxide semiconductor...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Laterally recessed tungsten silicide gate structure used...

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Layer arrangement

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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