Lateral MOSFET having a barrier between the source/drain regions

Details Lateral MOSFET having a barrier between the source/drain regions Lateral MOSFET having a barrier between the source/drain regions

1998-12-03

2000-10-03

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, H01L 21336

Patent

active

061272337

ABSTRACT:
A lateral MOSFET (100) and a method for making the same. A two layer raised source/drain region (106) is located adjacent a gate structure (112). The first layer (106a) of the raised source drain is initially doped p-type and the second layer (106b) of the raised source/drain region is doped n-type. P-type dopants from first layer (106a) are diffused into the substrate to form a pocket barrier region (105). N-type dopants from second layer (106b) diffuse into first layer (106a) so that it becomes n-type and into the substrate to form source/drain junction regions (104). P-type pocket barrier region (105) thus provides a barrier between the source/drain junction regions (104) and the channel region (108).

REFERENCES:
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patent: 5168072 (1992-12-01), Moslehi
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patent: 5270257 (1993-12-01), Shin
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patent: 5677214 (1997-10-01), Hsu
1990 IEEE, Symposium on VLSI Technology, "A New Structural Approach for Reducing Hot Carrier Generation in Deep Submicron MOSFESTs," pp. 43-44 (Al F. Tasch, Hyungsoon Shin and Christine M. Maziar).
IEEE Electron Device Letters, vol. 12, Mar. 1991, "Raised Source/Drain MOSFET With Dual Sidewall Spacers," pp. 89-91 (Mark Rodder, Member IEEE, and D. Yeakley).

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