Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-03-31
1999-03-23
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438306, 438307, 438297, 148DIG151, 148DIG126, H01L 218234
Patent
active
058858784
ABSTRACT:
To provide a lateral MISFET that has a uniform and reliable gate insulation film, and exhibits low on-resistance and excellent balance between the breakdown voltage and on-resistance. The device of the invention has an n-type semiconductor substrate, in a part of the surface layer thereof is formed a trench. An n-drain region is formed in the bottom of the trench. A side wall oxide film is formed on the side face of the trench. The trench is filled with a conductive material, on which is formed a drain electrode. A p-base region and an n-source region are self-aligned on the portion of the substrate in which the trench is not formed. A MIS gate is disposed on the p-base region. Since the portion of the substrate along the side wall oxide film functions as a drain drift region, the unit cell dimension are greatly reduced, the on-resistance is reduced, and therefore the trade-off relation between the breakdown voltage and the on-resistance is improved.
REFERENCES:
patent: 5272098 (1993-12-01), Smayling et al.
patent: 5434435 (1995-07-01), Baliga
patent: 5539238 (1996-07-01), Malhi
patent: 5701026 (1997-12-01), Fujishima et al.
Sakai et al., Technical Report, Japanese Institute of Electrical Engineers, 1992.
Fujishima Naoto
Kitamura Akio
Fuji Electric & Co., Ltd.
Murphy John
Niebling John F.
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