Latch-up prevention for memory cells

Details Latch-up prevention for memory cells Latch-up prevention for memory cells

1999-08-05

2002-04-23

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S200000, C438S202000

Reexamination Certificate

active

06376297

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to a static random access memory (SRAM), and, more particularly, to an SRAM having improved latch-up characteristics.
RAM chips are well known in the art. An SRAM chip is conventionally structured in rows and columns of individual SRAM cells. A prior art six transistor CMOS SRAM cell
1
is shown schematically in FIG.
1
. The SRAM cell
1
includes two n-type access transistors
5
,
6
, two p-type pull-up transistors
7
,
8
acting as load devices, and two n-type pull-down transistors
9
,
10
, with the pull-transistors
7
,
8
and pull-down transistors
9
,
10
forming two CMOS inverters. The SRAM cell
1
has two states: logic state “0” and logic state “1”. By convention, if logic state “0” is designated by node A having a high voltage and node B having a low voltage, then logic state “1” has the opposite stored voltages, i.e., node A having a low voltage and node B having a high voltage.
In logic state “0” the high voltage on node A turns on the pull-down transistor
9
and turns off the pull-up transistor
7
, whereas the low voltage on node B turns off the pull-down transistor
10
and turns on the pull-up transistor
8
. Because the pull-down transistor
9
is on and the pull-up transistor
7
is off, current flows through the pull-down transistor
9
to a voltage supply V
SS
(ground), thereby maintaining a low voltage on node B. Because the pull-up transistor
8
is turned on and the pull-down transistor
10
is turned off, current flows from a voltage supply V
CC
through the pull-up transistor
8
, thereby maintaining a high voltage on node A.
To change the state of the SRAM cell
1
from a logic “0” to a logic “1”, a column line
3
and a column line complement
2
are provided with a low and a high voltage, respectively. Then, the access transistors
5
and
6
are turned on by a high voltage on a row line
4
, thereby providing the low voltage on the column line
3
to node A and the high voltage on the column line complement
2
to node B. Accordingly, the pull-down transistor
9
is turned off and the pull-up transistor
7
is turned on by the low voltage on node A and the pull-down transistor
10
is turned on and the pull-up transistor
8
is turned off by the high voltage on node B, thereby switching the state of the circuit from logic “0” to logic “1”. Following the switching of the state of the SRAM cell
1
, the access transistors
5
and
6
are turned off (by applying a low voltage on row line
4
). The SRAM cell
1
maintains its new logic state in a manner analogous to that described above.
FIGS. 2A and 2B
are a schematic diagram and cross-section, respectively, of one of the CMOS inverters of
FIG. 1
illustrating parasitic transistors and resistors of the inverter. As shown in
FIG. 2B
, the pull-down transistor
9
is formed within a P-type substrate
12
while the pull-up transistor
7
is formed within an N-well
14
. The N-well
14
is formed within the P-type substrate
12
. The N-well
14
includes parasitic resistance denoted by the resistor
16
and the P-type substrate includes parasitic resistance denoted by the resistor
18
. The configuration of the pull-down transistor
9
and the pull-up transistor
7
results in the existence of a PNP parasitic bipolar transistor
20
and an NPN parasitic bipolar transistor
22
.
With the tight layout spacings that exist in a typical memory array, leakage currents from the N-well
14
and the P-type substrate
12
are possible. These leakage currents produce a voltage drop across the parasitic resistor
16
. If the voltage drop becomes sufficiently large, it can result in the parasitic PNP transistor
20
turning on and conducting current from the P+ region forming its emitter to the P-type substrate
12
that forms its collector. The P-type substrate
12
also forms the base terminal of the parasitic NPN transistor
22
and one terminal of the parasitic resistor
18
. The other terminal of the parasitic resistor
18
is the substrate tie-down represented by V
BB
. The current flowing through the resistor
18
produces a voltage rise at the point of injection. If this voltage rise becomes sufficiently large, it can result in the NPN transistor
22
turning on causing additional current to be drawn out the N-well
14
as collector current for the NPN transistor
22
. This additional current reinforces the original leakage from the N-well
14
turning the PNP transistor
20
on even harder providing added base current for the NPN transistor
22
. This feedback loop can result in a latch-up problem within the memory array containing the SRAM cell.
Accordingly, there is a need for an improved SRAM memory cell that is not prone to latch-up.
SUMMARY OF THE INVENTION
The present invention meets this need by providing an SRAM memory cell in which the source of the p-type pull-up transistor is coupled to V
CC
through the parasitic resistance of the N-well in which it is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.
According to a first aspect of the present invention, an SRAM memory cell is provided comprising a first pull-up transistor having a first substrate, a first source, a first gate coupled to a first node, and a first drain coupled to a second node. The first source is coupled to a first voltage input through parasitic resistance of the first substrate. A first pull-down transistor is provided having a second drain coupled to the second node, a second gate coupled to the first node, and a second source coupled to a second voltage source. An input line is coupled to the first node for providing a signal to the memory cell to change the memory cell from a first logic state to a second logic state. The input line may comprise an access transistor having one terminal coupled to the first node, another terminal coupled to a column line, and an access gate coupled to a row line.
According to another aspect of the present invention, an SRAM memory cell is provided comprising a first pull-up transistor, a first pull down transistor, a second pull-up transistor, a second pull-down transistor, and an input line. The first pull-up transistor includes a first substrate, a first source, a first gate coupled to a first node, and a first drain coupled to a second node. The first pull-down transistor includes a second drain coupled to the second node, a second gate coupled to the first node, and a second source coupled to a second voltage input. The second pull-up transistor includes a second substrate, a third source, a third gate coupled to the second node, and a third drain coupled to the first node. The second pull-down transistor includes a fourth drain coupled to the first node, a fourth gate coupled to the second node, and a fourth source coupled to the second voltage input. The first source is coupled to a first voltage input through parasitic resistance of the first substrate while the third source is coupled to the first voltage input through parasitic resistance of the second substrate. The input line is coupled to the first and second nodes for providing a signal to the memory cell to change the memory cell from a first logic state to a second logic state. Preferably, the first substrate and the second substrate are portions of a single substrate.
According to yet another aspect of the present invention, an SRAM memory cell is provided comprising a substrate assembly having at least one semiconductor layer, and a first semiconductor structure formed within the at least one semiconductor layer with the first semiconductor structure being coupled to a first voltage input. A first pull-up transistor is formed in the first semiconductor structure and comprises a first gate, a first source and a first drain. The first source is coupled to the first semiconductor structure such that the first source is coupled to the fir

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