Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-03
2001-02-13
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000, C438S301000
Reexamination Certificate
active
06187641
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
The following co-assigned co-pending patent applications are related to the invention and are hereby incorporated by reference:
Ser. No.
Filed
Inventors
08/957,503
10/24/97
Rodder et al.
08/957,193
10/24/97
Rodder et al.
09/205,346
12/3/98
Rodder
FIELD OF THE INVENTION
This invention generally relates to semiconductor devices and processes and more specifically to a lateral MOSFET structures having raised source/drain regions.
BACKGROUND OF THE INVENTION
As semiconductor devices are scaled to smaller dimensions, generally in the sub-0.1 &mgr;m region, it is highly desirable and generally necessary to fabricate such devices with smaller junction depths and a controllable pocket implant adjacent to the shallow junctions to reduce short-channel effects (i.e., reduced threshold voltage rolloff) and reduced in gate length. The pocket implant is a doped implanted region which is oppositely doped to the junction regions. A problem that arises with such small geometries is that, with very short channel lengths, the implant profile cannot be adequately controlled and shallow junctions and/or well controlled thicknesses of doped layers generally cannot be formed by simple implantation.
An example of such a prior art device is shown in
FIGS. 1
a
and
1
b
wherein there is shown a semiconductor substrate
1
, for example doped p-type, having a gate electrode
3
spaced from the substrate by a dielectric layer
5
. Shallow doped extension regions
7
(denoted herein as drain extension regions and, for example, doped n-type) may be formed on each side of the gate electrode
3
with or without sidewall dielectric spacers
2
provided adjacent to the gate electrode
3
prior to formation of the doped extension regions
7
. Pocket regions
9
of doping type opposite (e.g., p-type) to that of the drain extension regions
7
may be formed by means of implantation prior to or after formation of the drain extension regions
7
. Typically, the pocket region
9
extends beyond the drain extension regions
7
in both the lateral and vertical directions. whereby a large bottomwall capacitance can result due to the n/p junction region formed at the bottom of the drain extension region due to the overlap with the pocket region
9
over the entire active area. The doping in the pocket region
9
from the pocket process may be of higher concentration than the doping of the substrate
1
.
To reduce this bottomwall capacitance over the entire active area, a deeper source/drain region
10
(in this example, n-type) can be formed after formation of sidewall spacers
12
so that the bottomwall overlap of the deeper source/drain region
10
and the pocket regions
9
is eliminated, thus reducing the bottomwall capacitance in these regions as shown in
FIG. 1
b.
When dealing with sub-0.1 &mgr;m geometries, the gate width dimensions are in the 200 to 900 angstrom region, thereby leaving a channel region on the order of about 100-800 angstroms. Implants cannot be adequately controlled in accordance with the prior art semiconductor fabrication techniques when such small dimensions are involved.
REFERENCES:
patent: 4853342 (1989-08-01), Taka et al.
patent: 5168072 (1992-12-01), Moslehi
patent: 5736419 (1998-04-01), Naem
patent: 5872039 (1999-02-01), Imai
patent: 6057200 (2000-05-01), Prall et al.
Sidek et al, “Reduction of parasitic bipolar transistor action and punchthrough susceptibility in MOSFETs using Si/Si(1-x)Ge(x) sources and drains,” Election Letters, vol. 32, No. 3, pp. 269-270, Feb. 1, 1996.
Unchino et al “A raised source/drain technology using in-situ P-doped SiGe and B-doped Si for 0.1 micron CMOS ULSIs” IEEE IEDM 97, pp. 479-482, 1997.
1990 IEEE, Symposium on VLSI Technology, “A New Structural Approach for Reducing Hot Carrier Generation in Deep Submicron MOSFESTs,” pp. 43-44 (Al F. Tasch, Hyungsoon Shin and Christine M. Maziar).
Liu William U.
Rodder Mark S.
Brady III W. James
Garner Jacqueline J.
Hach Jonathan
Niebling John F.
Telecky , Jr. Frederick J.
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