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Scan test circuit including a control test mode

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan test circuit with reset control circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan test circuit, semiconductor integrated circuit and scan...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan test circuitry using a state machine and a limited...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan test control method and scan test circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan test expansion module

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan test method for providing real time identification of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan test system for semiconductor device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan testable circuit arrangement

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan testable circuit arrangement

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan testable register file

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan testing architectures for power-shutoff aware systems

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan testing methods

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan testing mode control of gated clock signals for flip-flops

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan testing mode control of gated clock signals for memory...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan testing of integrated circuits with high-speed serial...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan testing of integrated circuits with high-speed serial...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan testing system for circuits under test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan testing using scan frames with embedded commands

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Scan tests tolerant to indeterminate states when employing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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