Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-01-24
2010-06-15
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C710S033000
Reexamination Certificate
active
07739566
ABSTRACT:
An electronic circuit includes a group of devices which facilitate scan testing of at least one part of the electronic circuit. Those devices include a scan test device. The circuit further includes a state machine which operates to transfer data from an input pin of the circuit which is dedicated to the state machine to the devices relating to scan testing. The state machine supports a plurality of data transfer protocols. The choice of the protocol to be used is made as a function of a signal received on the input pin. Responsive to an input pin signal, the state machine enters an operational mode wherein scan test programming data is serially received at the input pin and communicated to the devices which facilitate scan testing. More specifically, the scan test programming data is serially communicated to a scan test register, where the data is output in parallel to the scan test device.
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Preliminary French Search Report, FR 06 00787, dated Dec. 5, 2006.
Britt Cynthia
Gardere Wynne & Sewell LLP
STMicroelectronics S.A.
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