Scan testable circuit arrangement

Details Scan testable circuit arrangement Scan testable circuit arrangement

2000-03-17

2001-10-16

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C370S241000, C370S911000

Reexamination Certificate

active

06304988

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to circuit arrangements for functionally testing logic circuits, and more particularly to a circuit arrangement for utilizing a common bus for functional operations of the logic circuits and for scan testing the logic circuits.
BACKGROUND
Testing a logic circuit is often performed by loading test data into the logic circuit and, in a controlled manner, advancing the logic circuit from state to state. Various test data is output from the logic circuit and examined to determine whether the logic circuit is functioning as expected. Special scan test input/output pins are often provided for the input and output of the test data. Both parallel and serial designs exist for scanning-in and scanning-out test data via the scan test input/output pins. Parallel designs decrease the time required to load test data and read test results at the expense of increased pin resources. Serial designs conserve pin resources, but require additional time to load test data and read test results as compared to parallel designs.
Increasing levels of circuit integration create at least two problems for scan testing logic circuits. First, as the number of functional blocks of logic circuits on a chip increases, the length of scan paths and the quantity of test data increase. Increased scan paths create layout complexity and increase costs, and more test data typically leads to increased test complexity. A second problem is that a greater number of functional blocks of logic circuits on a chip creates increased demand for input/output pins for circuit access during normal operation, thereby competing with input/output pins used exclusively for scan testing.
Cost-effective and efficient solutions for scan testing are highly desirable for the aforementioned reasons. However, present designs often trade pin resources against test time in implementing a desired level of cost-effectiveness and efficiency.
SUMMARY
The present invention is generally directed to a circuit arrangement and method that provides for functional testing of logic circuits, where a common bus is used for both a test mode and for a normal operational mode.
Consistent with one aspect of the present invention, a scan testable circuit arrangement includes a bus; a plurality of logic circuits having scan test ports; input/output ports; a first plurality of switches, each having a first terminal coupled to a predetermined signal line of the bus and a second terminal coupled to a respective one of scan test ports of the logic circuits; a second plurality of switches, each having a first terminal coupled to a predetermined signal line of the bus and a second terminal coupled to a respective one of input/output ports of the logic circuits; and a plurality of command decoders coupled to the bus for receiving bus commands and coupled to the gates of the first and second plurality of switches, responsive to a first set of commands for coupling the scan test ports to the bus for a first operational mode, and responsive to a second set of commands for coupling the input/output ports to the bus for a second operational mode.
In another aspect of the invention, the scan test ports of each of the logic circuits are switchably coupled to a predetermined set of lines of the bus, each set respectively dedicated to one of the logic circuits.
Consistent with yet another aspect of the invention, the logic circuits are organized into a plurality of groups, each group including predetermined ones of the logic circuits and predetermined ones of the command decoders, the first set of bus commands including respective codes for specifying each of the groups and the command decoders responsive to the respective codes, whereby each group is individually selectable for scan testing.
In yet another aspect of the invention, the plurality of scan test ports include scan enable ports and scan clock ports, scan-in data ports, and scan-out data ports, the scan enable ports of the logic circuits switchably coupled to a predetermined first line of the bus, the scan clock ports of the logic circuits switchably coupled to a predetermined second line of the bus, the scan-in data port of a predetermined first one of the logic circuits switchably coupled to a predetermined third line of the bus, the scan-out data port of the first one of the logic circuits switchably coupled to a predetermined fourth line of the bus, the scan-in data port of each of the others of the logic circuits switchably coupled to the scan-out data port of another of the logic circuits via one of the lines of the bus, and the scan-output port of a predetermined last one of the logic circuits switchably coupled a predetermined fifth line of the bus.
According to another aspect of the invention, a method is provided for scan testing logic circuits. The method involves transitting via a first bus a first command code to logic circuits that are coupled to the first bus; coupling scan test ports of the logic circuits to the first bus in response to the first command code; decoupling input/output circuits of the logic circuits from the first bus in response to the first command; inputting predetermined test data to the logic circuits via the bus; outputting data resulting from a test via the first bus; transmitting via the first bus a second command code to the logic circuits; decoupling scan test ports of the logic circuits from the first bus in response to the second command; and coupling input/output circuits of the logic circuits to the first bus in response to the second command.
The above summary of the present invention is not intended to provide an overview of each illustrated embodiment of the present invention. From the figures and the detailed description which follow, other advantages and aspects of the present invention will become apparent.


REFERENCES:
patent: 4357703 (1982-11-01), Brunt
patent: 4625310 (1986-11-01), Mercer
patent: 4926424 (1990-05-01), Maeno
patent: 5161160 (1992-11-01), Yaguchi et al.
patent: 5471481 (1995-11-01), Okumoto et al.
patent: 6041427 (2000-03-01), Levy

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