Scan test circuit, semiconductor integrated circuit and scan...

Details Scan test circuit, semiconductor integrated circuit and scan... Scan test circuit, semiconductor integrated circuit and scan...

2008-03-05

2010-11-16

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000, C714S729000

Reexamination Certificate

active

07836370

ABSTRACT:
A SCAN test circuit for giving a semiconductor integration circuit a scan test includes a scan enable signal generating device that generates scan enable signals based on a scan enable external input signal, a clock generator that generate launch and capture clocks for collectively detecting a delay malfunction at a practical operation speed, and a controller configured to control the clock generator based on the scan enable signals.

REFERENCES:
patent: 7202656 (2007-04-01), Gearhardt et al.
patent: 7444567 (2008-10-01), Wang et al.
patent: 2005/0240846 (2005-10-01), Madpuwar et al.
patent: 2008/0010573 (2008-01-01), Sul
patent: 2008/0126898 (2008-05-01), Pandey
patent: 2001-221836 (2001-08-01), None
patent: 2006-65339 (2006-03-01), None

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