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Selected: M

Mechanism to provide test access to third-party macro...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Mechanism to simplify built-in self test of a control store...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Mechanism to stop instruction execution at a microprocessor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Mechanisms for detecting silent errors in streaming media...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Media converter and failure detection technique

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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Medium reading apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Meeting point thread characterization

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Memory access control device, and its control method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Memory access system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Memory address generating apparatus, processor having the...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Memory address generator in convolutional interleaver/deinterlea

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent

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Memory analyzing apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory and method for checking reading errors thereof

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Memory apparatus and data processor using the same

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Patent

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Memory apparatus and method and reduced pin count apparatus...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory architecture for automatic test equipment using...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Memory array manufacturing defect detection system and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Memory array manufacturing defect detection system and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Memory array organization

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Memory array repair where repair logic cannot operate at...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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