Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1994-09-01
2001-09-04
Trammell, James P. (Department: 2161)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06286120
ABSTRACT:
This invention relates generally to automatic test equipment d more particularly to memory architecture for the pattern generating portion of automatic test equipment.
Automatic test equipment (called simply a “tester”) is used to test electronic components and devices as they are being manufactured. The tester has numerous signal lines (called “channels”) which connect to the device under test (“DUT”). Stimulus signals are placed on some of these lines and the response of the DUT is measured on other lines. By comparing the response received from the DUT to an expected response, faults in the DUT may be detected.
State of the art test systems are controlled by very fast computers which run programs called “patterns.” The pattern contains information about the stimulus signals that should be applied, the order in which those signals should be applied and the expected response from the DUT. This information for any cycle of the tester is called a “vector.” The pattern is, thus, made up of a series of vectors. A typical pattern for a tester designed to test VLSI components can have over one million vectors.
Testers must run at state of the art speeds for several reasons. First, it is desirable that each test be completed as quickly as possible since manufacturers want to produce as many parts as quickly as possible. Secondly, certain types of faults in components are not detectable unless the device is operated at its intended operating speed. To enable the tester to run at state of the art speeds, the patterns are stored in very fast RAM memories.
Testers use vast amounts of RAM. A typical tester needs to store around four million vectors. Each vector contains several bits of data for each channel in the tester. Up to 512 channels is a typical number of channels in a tester. In addition, each vector contains several bits of control information. The net result is that a tester typically contains in the range of 750 Mbytes of RAM. Using only the most advanced RAM for all this memory would result in a tester which would be too expensive.
Rather, there is a speed/cost/flexibility tradeoff associated with selecting RAM. Flexibility refers to the range of memory addresses which can be accessed in consecutive memory cycles. Maximum flexibility occurs when any address can be accessed on any cycle. Minimum flexibility occurs when only addresses in sequence may be accessed on consecutive cycles. Higher speed memories for a given flexibility level cost more. Likewise, higher performance memories operating at a given speed cost more.
Typically, flexibility has been sacrificed to get good speed at reasonable cost. In the tester, vectors are executed in exactly the order they have been written into the pattern memory. Users of testers would prefer not to have such a limitation. It is sometimes difficult to develop a full pattern in exactly the order it is to executed. Test engineers usually prefer to approach the problem of writing a test pattern by segmenting the DUT into various functional elements and writing a pattern to test each functional element. Requiring sequential execution of vectors in memory also implies that control constructs such as looping and branching may not be used in the pattern. A further disadvantage of sequential execution occurs because some steps needed to test different functional elements or to perform different tests on one functional element will often be the same. For example, it will often be necessary to perform an initialization sequence repeatedly on the DUT as it is fully tested. If a pattern may only be executed in the order it is written into memory, the initialization sequence must be written into the memory every time it is used. Making multiple copies of the same set of vectors wastes space in the memory and also makes it difficult for the test engineer to change the test pattern because every copy must be changed.
Some flexibility may be obtained because the tester is usually connected to and controlled by a computer work station. The work station contains bulk storage media, such as a disk or magnetic tape, that can inexpensively store large amounts of data. Different patterns can be developed and stored on the work station and then loaded into the tester when needed to perform a test.
To facilitate making different patterns, vectors are usually grouped into modules. Each module is a collection of vectors which performs one or more functions. For example, one module might contain vectors to initialize the DUT. Another module might contain vectors to test registers inside the DUT and yet another module might contain vectors to test arithmetic logic circuitry inside the DUT. To make a pattern, these modules could be linked together on the work station and then loaded into the pattern memory of the tester.
The use of modules has the further advantage of allowing a complicated pattern to be broken into pieces which can be more easily developed and debugged. However, it does not fully solve the problem. The process of loading a new pattern from the work station can take many minutes. Since the tester is used in a manufacturing operation to test many parts as rapidly as possible, a delay of a few minutes for each part tested would add an unacceptable delay. Use of a work station also does not eliminate memory waste caused by repeating sequences of vectors in the code. It also does not allow branching, looping or similar nonsequential control constructs.
Limited nonsequential control constructs have been incorporated into testers by allowing only those control constructs in which the address for the next vector to be executed is limited to one of a very small number of possibilities. One such approach has been to allow a given vector from the pattern memory to be executed a specified number of times before the next vector in sequence is executed. This approach provides a useful feature in that it reduces the number of vectors that have to be stored in a pattern memory for some types of patterns. It also does not unduly complicate the tester circuitry because the memory address for the next vector to be executed could have only one of two values: the same as the current address or one address higher. This approach does not allow the tester to execute groups of vectors repeatedly or in any order different from the order in which they have been placed in the pattern memory.
Another approach to providing greater flexibility while still limiting the number of choices for the next address is to provide multiple memories. One of the memories can be programmed to contain groups of vectors that are repeated in the test pattern, much like a subroutine in traditional computer programming. During execution of the pattern, the vectors in the first memory are executed in sequence until a vector is reached which indicates that the “subroutine” vectors should be executed from a different memory. Execution of vectors switches over to the second memory until a vector is reached which indicates execution of vectors should resume from the first memory. Thereafter, the vectors in the first memory are executed sequentially. There is no limit on the number of times that the vectors in the subroutine memory can be executed, thereby reducing the need to repeat those vectors at multiple places in the pattern.
Variations on this approach are possible. U.S. Pat. No. 4,502,127 to Garcia describes a variation where vectors may be developed by taking data from both the large memory and the subroutine memory simultaneously. Japanese patent publication 52-144125 describes a variation where the “subroutine” is implemented in a different region of the same memory as the main pattern. All of these approaches reduce the amount of memory needed to store a pattern.
The need to provide more flexibility in the order of execution of vectors can also be addressed by using multiple memories. In some commercial systems, one memory is very large and inflexible. A second memory is much more flexible and allows branching and looping, but is very small.
Various implementations of this basic approach a
Brown Benjamin J.
Reichert Peter A.
Elisca Pierre E.
Teradyne, Inc.
Trammell James P.
Walsh Edmund J.
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