Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1998-05-22
2000-10-24
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
714786, G11C 2900
Patent
active
061382620
ABSTRACT:
A memory address generator in a convolutional interleaver/deinterleaver for correcting errors occurred in a data transmission of communication systems. The memory address generator includes: a first counter for counting a first variable (y) representing a location of one of total rows in a memory of the convolutional interleaver/deinterleaver, in response to a clock signal; a second counter for counting a second variable (z) representing a location of one of total columns in the memory of the convolutional interleaver/deinterleaver; a third counter for counting a third variable (x) representing a location of the memory address in an unit memory cell having a plurality of a memory address; an offset value generator for generating an offset value of the first variable in response to the first variable; a first adder for adding the second variable outputted from the second counter to the third variable outputted from the third counter; and a second adder for adding the added value from the first adder to the offset value of the first variable outputted from the offset value generator and outputting the memory address of the convolutinal interleaver/deinterleaver.
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Cady Albert De
Hyundai Electronics Industries Co,. Ltd.
Ton David
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