Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-03-07
2010-02-16
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C709S241000
Reexamination Certificate
active
07665000
ABSTRACT:
An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run.
REFERENCES:
patent: 6389449 (2002-05-01), Nemirovsky et al.
patent: 6789100 (2004-09-01), Nemirovsky et al.
patent: 7020879 (2006-03-01), Nemirovsky et al.
patent: 7467385 (2008-12-01), Nemirovsky et al.
patent: 7584342 (2009-09-01), Nordquist et al.
Cai Qiong
Chaparro Pedro
Gonzalez Antonio
Gonzalez Jose
Magklis Grigorios
Intel Corporation
Ton David
Trop Pruner & Hu P.C.
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