Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2005-08-09
2005-08-09
Chung, Phung My (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
06928595
ABSTRACT:
The configuration of a microcomputer to be used as the control device of a medium reading apparatus is such that writing unit by unit into and erasion block by block from a prescribed area, such as a user data storage area, in a nonvolatile memory built into the microcomputer makes possible, if any writing into the user data storage area is needed, for data to be successively written while updating the units, data included in the prescribed area to be erased when all the units have been written into, and the next data to be written into the erased blocks.
REFERENCES:
patent: 5608891 (1997-03-01), Mizuno et al.
patent: 6393561 (2002-05-01), Hagiwara et al.
patent: 6493271 (2002-12-01), Matsubara et al.
patent: 6690603 (2004-02-01), Matsubara et al.
Iso Yoshimi
Takahashi Hiromasa
Yamato Satoshi
Chung Phung My
Hitachi ULSI Systems Co. Ltd.
Miles & Stockbridge P.C.
Renesas Technology Corp.
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