Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-09-26
2008-12-30
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S034000
Reexamination Certificate
active
07472323
ABSTRACT:
A method and apparatus for stopping the internal clock of a microprocessor synchronously with the execution of an instruction is provided. A stop instruction is placed in a sequence of instructions to be executed by the microprocessor. The execution of the stop execution may store a stop value into a stop register of the microprocessor. Clock stop logic detects when the stop value has been stored into the stop register. The clock stop logic instructs a clock generation component, of the microprocessor, to cease generation of an internal clock signal, thereby preventing the microprocessor from changing state. As further instructions are not executed by the microprocessor, the state of the microprocessor reflects the execution of the instruction immediately prior to the stop instruction. The processing state of the microprocessor may be obtained for use in debugging the design of the microprocessor or the instructions executed thereby.
REFERENCES:
patent: 5675282 (1997-10-01), Saito
patent: 6088807 (2000-07-01), Maher et al.
patent: 6118306 (2000-09-01), Orton et al.
patent: 6336195 (2002-01-01), Shen et al.
Diraviam Senthilkumar
Greenley Dale Robert
Narasimhaiah Chitresh Chandra
Britt Cynthia
Gandhi Dipakkumar
Hickman Palermo & Truong & Becker LLP
Sun Microsystems Inc.
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