Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2011-01-25
2011-01-25
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S718000, C714S799000, C714S047300, C714S005110, C714S006130, C714S052000, C714S754000, C714S002000, C711S102000, C365S148000, C365S201000, C365S222000
Reexamination Certificate
active
07877668
ABSTRACT:
When a host system outputs a read command to a memory controller, it measures a load count of a memory area on which a read access load is imposed. Then, when the host system judges that the load count of a memory area reaches a predetermined count, it causes the memory controller to perform an error detection on the memory area. Further, when the host system finds that an error occurs in the memory area, it causes the memory controller to perform an error correction on the memory area. This can avoid or reduce unintended rewriting due to repeated readouts.
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U.S. Appl. No. 12/170,102, filed Jul. 9, 2008, Sugahara.
Megachips Corporation
Oblon, Spivak, McClelland. Maier & Neustadt, L.L.P.
Trimmings John P
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