Memory access system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Details

C714S718000, C714S799000, C714S047300, C714S005110, C714S006130, C714S052000, C714S754000, C714S002000, C711S102000, C365S148000, C365S201000, C365S222000

Reexamination Certificate

active

07877668

ABSTRACT:
When a host system outputs a read command to a memory controller, it measures a load count of a memory area on which a read access load is imposed. Then, when the host system judges that the load count of a memory area reaches a predetermined count, it causes the memory controller to perform an error detection on the memory area. Further, when the host system finds that an error occurs in the memory area, it causes the memory controller to perform an error correction on the memory area. This can avoid or reduce unintended rewriting due to repeated readouts.

REFERENCES:
patent: 4694454 (1987-09-01), Matsuura
patent: 2005/0210184 (2005-09-01), Chen et al.
patent: 2007/0011513 (2007-01-01), Biswas et al.
patent: 2007/0214395 (2007-09-01), Shiota et al.
patent: 2008/0117663 (2008-05-01), Philipp et al.
patent: 2009/0055680 (2009-02-01), Honda et al.
patent: 2009/0125671 (2009-05-01), Flynn et al.
patent: 8-279295 (1996-10-01), None
patent: 08-279295 (1996-10-01), None
patent: 2000-235524 (2000-08-01), None
U.S. Appl. No. 12/170,102, filed Jul. 9, 2008, Sugahara.

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