Memory apparatus and method and reduced pin count apparatus...

Details Memory apparatus and method and reduced pin count apparatus... Memory apparatus and method and reduced pin count apparatus...

2007-06-11

2011-12-06

Gaffin, Jeffrey A (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S716000, C714S723000

Reexamination Certificate

active

08074129

ABSTRACT:
A memory apparatus is disclosed, comprising a memory device under test, a reduced-pin-count device and a built-in self test device. The reduced-pin-count device is used to find a faulty cell address in the memory device under test during a pre-fuse stage. The built-in self test device is used to detect whether the memory device under test has any error during a post-fuse stage. The memory apparatus is capable of promptly finding the address of a defect cell in the memory device under test such that repairs can be performed during a fuse stage. Furthermore, the invention reduces the pin count required during testing the memory device under test. Thus, the cost of testing equipment is reduced and the performance of memory testing is enhanced.

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