Memory array manufacturing defect detection system and method

Details Memory array manufacturing defect detection system and method Memory array manufacturing defect detection system and method

2008-01-08

2008-01-08

Lamarre, Guy (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000, C714S030000, C714S719000, C714S734000, C714S736000, C365S201000

Reexamination Certificate

active

11002692

ABSTRACT:
The present invention provides for a method for memory array verification. Initialization commands are received and memory array initialization settings are generated based on received initialization commands. The memory array initialization settings are stored in a memory array. A deterministic read output function for the memory array is identified and a logic built-in self test scan on the memory array is performed based on the identified deterministic read output function.

REFERENCES:
patent: 5173906 (1992-12-01), Dreibelbis et al.
patent: 6543019 (2003-04-01), Kniffler et al.
patent: 6560740 (2003-05-01), Zuraski et al.

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