Memory analyzing apparatus

Details Memory analyzing apparatus Memory analyzing apparatus

1997-08-28

2000-02-22

Chung, Phung M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714718, G11C 2900

Patent

active

060292601

ABSTRACT:
When defective bits of a memory are remedied, the disclosed memory analyzing apparatus can execute remedy analysis of a large capacity memory freely and effectively in a short time. Data are transferred from a defect cell memory (3) provided for a memory tester body (1) to a remedy analyzing apparatus (2) in the sequence suitable for defect remedy. The transferred data are regenerated in address sequence, and the numbers of the defective bits are counted and stored in an X line defect memory (26) and a Y line defect memory (27) at the same time. Further, a line detect flag is raised on the basis of the number of detective bits in the same row and the same column. Further, with respect to the defective bits of a line other than the defect line, the addresses thereof are stored in the bit defect memory (35), and the number of the defect bits is stored in a unit region defect number memory (33) for each defect remedy unit region. A CPU (5) allocates remedy lines to the line defects with a priority, and further processes the allocation analysis of the remedy lines on the basis of the data obtained from the respective memories (26, 27, 33, and 35), so that it is possible to reduce the remedy processing time markedly.

REFERENCES:
patent: 5400342 (1995-03-01), Matsumura et al.

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