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Implementation of an assertion check in ATPG models

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Implementation of boolean satisfiability with non-chronological

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Implementation of LDPC (low density parity check) decoder by...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Implementation of signature analysis for analog and mixed...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Implementation of test patterns in automated test equipment

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Implementation of variable bit density recording in storage...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
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Implementing diagnosis of transitional scan chain defects...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Implementing enhanced array access time tracking with logic...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Implementing enhanced LBIST testing of paths including arrays

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Implementing isolation of VLSI scan chain using ABIST test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Implementing minimized latency and maximized reliability...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Implied interleaving a family of systematic interleavers and dei

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent

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Impulse noise mitigation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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In situ processor margin testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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In system diagnostics through scan matrix

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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In-chip monitoring system to monitor input/output of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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In-flight programmable spacecraft error correction encoder

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate

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In-line wire error correction

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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In-service raid mirror reconfiguring

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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In-system programmable flash memory device with trigger...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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