Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1998-04-10
1999-10-19
Moise, Emmanuel L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
714701, 714702, 711157, G06F 1110, H03M 1312
Patent
active
059682000
ABSTRACT:
Apparatus that realizes a substantial advantage by employing implied interleaving to create a systematic interleaver, that can result in a superior block error rate compared to the current data interleaving techniques in which uncorrected error bursts are distributed by the deinterleaver. The disclosed principles lead to a embodiments that essentially eliminate transmitter memory regardless of the interleaving approach employed. By way of example, block interleaving (regular or random), convolutional interleaving (regular and random) and product interleaving approaches are described. In implied interleaving, all incoming data is treated as if it is pre-interleaved and transmitted directly to its destination without alteration to its sequence, and essentially without delay. Concurrently with the transmission of the data, the data is applied to apparatus that treats the data as if it had been interleaved in accordance with a selected interleaving approach and, in accordance with such treatment, redundant symbols are generated and inserted into the transmitted data stream. At the receiver, the incoming data is delayed, corrected, and the information symbols in the incoming data are delivered to the user, corrected as necessary, in the same order as the information symbols arrived at the receiver.
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Globespan Technologies, Inc.
Moise Emmanuel L.
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