Implementing minimized latency and maximized reliability...

Details Implementing minimized latency and maximized reliability... Implementing minimized latency and maximized reliability...

2011-07-19

2011-07-19

Abraham, Esaw T (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S005110, C365S185090

Reexamination Certificate

active

07984357

ABSTRACT:
A memory controller and methods implement minimized latency and maximized reliability when data traverses multiple buses. The memory controller includes a dynamic random access memory (DRAM) error correcting code (ECC) checking and correcting circuit and a high speed bus (HSB) ECC checking and correcting circuit. In a first mode for implementing minimized latency, read data is applied directly to the DRAM ECC checking and correcting circuit, bypassing the HSB ECC checking and correcting circuit. In a second mode for implementing maximized reliability, the read data is applied through the HSB ECC checking and correcting circuit to the DRAM ECC checking and correcting circuit.

REFERENCES:
patent: 6397357 (2002-05-01), Cooper
patent: 7167410 (2007-01-01), Boecker et al.
patent: 7461320 (2008-12-01), Klein
patent: 7516371 (2009-04-01), Sakaue et al.
patent: 7624329 (2009-11-01), Syzdek et al.
patent: 7779334 (2010-08-01), Earle et al.

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