Structure and method for improving storage latch...
Structure and method of using asymmetric junction engineered...
Structure for a configurable SRAM system and method
Structure for cross coupled thin film transistors and static ran
Structure of static random access memory with stress...
Substrate-fed injection-coupled memory
Suppression of leakage currents in VLSI logic and memory...
Swapped-body RAM architecture
Switch device and method
Switch device and method
System and method for enabling/disabling SRAM banks for...
System and method for forcing an SRAM into a known state...
System and method for preserving an error margin for a...
System and method for writing to and reading from a memory cell
System for bitcell and column testing in SRAM
System, apparatus, and method to increase read and write...
Systems and devices for implementing sub-threshold memory...
Systems and methods for improving memory reliability
Tamper memory cell
Techniques for reducing power consumption in memory cells