Swapped-body RAM architecture

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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Details

C365S156000, C365S189090, C365S226000, C365S227000, C365S228000, C365S229000

Reexamination Certificate

active

07742325

ABSTRACT:
A method for operating an SRAM cell comprises, during a read operation, forward biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during a write operation, zero or reverse biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during an idle state, zero biasing an N-well of a first and second pull-up transistor and zero biasing a P-well of a first and second pull-down transistor and a first and second access transistor. In addition, one or more rows or columns of memory cells may receive a bias voltage.

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PCT Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authorityfor International Application No. PCT/US2008/083531; 13 pages, Feb. 16, 2009.

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