System and method for forcing an SRAM into a known state...

Details System and method for forcing an SRAM into a known state... System and method for forcing an SRAM into a known state...

2000-01-04

2008-10-07

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C713S002000, C365S095000, C365S103000, C365S189090

Reexamination Certificate

active

07433224

ABSTRACT:
There is disclosed a static random access memory (SRAM) device that stores an embedded program that is accessible when the SRAM device is powered up. The SRAM device comprises a plurality of storage cells, each of the storage cells comprises a data latch having an input and an output, wherein the data latch comprises a) a first inverter having an input coupled to the first I/O line and an output coupled to the second I/O line, and b) a second inverter having an input coupled to the second I/O line and an output coupled to the first I/O line. The storage cell also comprises a biasing circuit that forces at least one of the first and second I/O lines to a known logic state when power is applied to the SRAM device. The known logic state comprises one bit in the embedded program.

REFERENCES:
patent: 4777623 (1988-10-01), Shimazu et al.
patent: 5365475 (1994-11-01), Matsumura et al.
patent: 5434811 (1995-07-01), Evans, Jr. et al.
patent: 5923582 (1999-07-01), Voss
patent: 06060667 (1994-03-01), None

Affiliated with

Also associated with

Rating

System and method for forcing an SRAM into a known state... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for forcing an SRAM into a known state..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for forcing an SRAM into a known state... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4014581