System for bitcell and column testing in SRAM

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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Details

C365S156000, C365S204000, C365S189070

Reexamination Certificate

active

08085580

ABSTRACT:
A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The transistor is activated while the storage cell is read.

REFERENCES:
patent: 5781469 (1998-07-01), Pathak et al.
patent: 7042780 (2006-05-01), Lee
patent: 2006/0039180 (2006-02-01), Kawasumi

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