Switch device and method

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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C365S185230, C365S230060

Reexamination Certificate

active

11373532

ABSTRACT:
A device is disclosed having a first Field Effect Transistor having a channel region controlled by a gate, a second Field Effect Transistor having a first channel region substantially controlled by a first gate, and a second channel region substantially controlled by a second gate. The gate of the first Field Effect Transistor and the first gate of the second Field Effect Transistor are coupled to a memory write line. The second gate of the second Field Effect Transistor receives a control signal from a memory bit cell.

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patent: 2006/0274569 (2006-12-01), Joshi et al.
Guo et al., “FinFET-Based SRAM Design,” Department of Electrical Engineering and Computer Sciences, University of California, Berkeley California, pp. 2-7.
Yamaoka et al., “Low Power SRAM Menu for SOC Application Using Yin-Yang-Feedback Memory Cell Technology,” 2004 IEEE, 2004 Symposium On VLSI Circuits digest of Technical Papers, Tokyo Japan, pp. 288-291, 2004.
Actions on the Merits by the U.S.P.T.O. as of Nov. 29, 2007, 1 page.
International Search Report for correlating PCT Application No. PCT/US07/62196 dated Apr. 1, 2008.
Actions on the Merits by the U.S.P.T.O. as of Apr. 8, 2008, 1 page.

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