System and method for enabling/disabling SRAM banks for...

Details System and method for enabling/disabling SRAM banks for... System and method for enabling/disabling SRAM banks for...

2000-02-17

2001-09-04

Elms, Richard (Department: 2759)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S203000, C365S189110

Reexamination Certificate

active

06285579

ABSTRACT:

TECHNICAL FIELD
This invention relates in general to memory architecture, and in particular to circuitry for enabling/disabling SRAM memory for read/write operations.
BACKGROUND
Static random access memory (SRAM) is commonly utilized in prior art computer systems for storing data. Generally, SRAM memory is a type of memory that is very reliable and very fast. Unlike dynamic random access memory (DRAM), SRAM does not need to have its electrical charges constantly refreshed. As a result, SRAM memory is typically faster and more reliable than DRAM memory. For example, while DRAM supports access times (i.e., the time a program or device takes to locate a single piece of information and make it available to the computer for processing) of about 60 nanoseconds, SRAM of the prior art may provide access times as low as 10 nanoseconds. In addition, SRAM's cycle time (i.e., a measurement of how quickly two back-to-back accesses of a memory chip can be made) is typically much shorter than that of DRAM because it does not need to pause between accesses. Unfortunately, SRAM memory is generally much more expensive to produce than DRAM memory. Due to its high cost, SRAM is typically implemented only for the most speed-critical parts of a computer, such as the memory cache. However, SRAM memory may be implemented for other memory components of a computer system, as well.
FIG. 1
illustrates a typical SRAM cell
100
of the prior art. The SRAM structure of
FIG. 1
is a typical 6-T (6 transistor) SRAM cell comprising field effect transistors (FETs)
102
,
104
,
106
,
108
,
110
, and
112
. The SRAM structure
100
of
FIG. 1
is well-known in the art and is commonly implemented in integrated circuits of the prior art. The SRAM cell
100
of
FIG. 1
is a memory cell capable of storing one bit of data (i.e., a logic 1 or a logic 0). Thus, many of such SRAM cells
100
are typically implemented within a system to provide the desired amount of SRAM memory. As shown, a BIT line, WORD line, and NBIT line are typically included in the structure
100
. The BIT line, which may also be referred to herein as a “data carrier,” is a line on which data to be read from or written to the SRAM cell
100
is placed, and the NBIT line, which may also be referred to herein as a “complementary data carrier,” is the complement (opposite voltage value) of the BIT line. Typically, the BIT line is held to a high voltage level (i.e., a logic 1), unless it is actively pulled to a low voltage level (i.e., a logic 0). For instance, when writing data to the SRAM cell
100
, the BIT line is actively driven low by an outside source (e.g., an instruction being executed by the processor) if the outside source desires to write a 0 to the SRAM cell
100
. Otherwise, if an outside source desires to write a 1 to the SRAM cell
100
, the BIT line remains high. Thereafter, the WORD line is fired (e.g., caused to go to a high voltage level), at which time the value of the BIT line is written into the SRAM cell
100
.
When reading data from the SRAM cell
100
, the WORD line is fired, and the BIT line is driven by the SRAM cell. That is, the BIT line is pulled low by the SRAM cell
100
if the data stored therein is a 0, and the BIT line remains high if the value stored in the SRAM cell
100
is a 1. More specifically, when reading data from the SRAM cell
100
, the BIT line is pulled to a low voltage value by N-channel FET (NFET)
102
if the data stored in the SRAM cell
100
is a 0. However, if the value stored in the SRAM cell
100
is a 1, the BIT line remains at a high voltage value.
Typically, many SRAM cells, such as SRAM cell
100
, are connected to a single BIT line. For example, 256 SRAM cells are commonly connected to a single BIT line. As a result, a full rail discharge does not occur quickly on the BIT line when it is pulled to a 0. That is, when the BIT line is being pulled low for a particular SRAM cell, the other 255 SRAM cells connected to the BIT line present more capacitance (i.e., parasitic capacitance) on the BIT line, thereby preventing it from discharging quickly. Thus, for example, if one SRAM cell is attempting to drive the BIT line to a low voltage value (logic 0), the other SRAM cells connected to the BIT line may present capacitance on the BIT line thereby preventing it from fully discharging to a low voltage value quickly. Because the capacitance resulting from the many SRAM cells connected to a BIT line may effect the value that is achieved for a particular SRAM cell, circuitry is required in prior art implementations to detect whether a particular voltage level is a logic 1 or a logic 0. That is, because the BIT line can not fully discharge to provide a “true” 0, circuitry is required to determine whether a detected value on the BIT line is to be interpreted as a 0. Thus, a sense amp is typically utilized in prior art designs to detect whether the value on the BIT line is a logic 1 or a logic 0 by recognizing slight value changes in the BIT line. More specifically, such a sense amp determines whether a value on the BIT line is to be interpreted as a logic 0 or logic 1, and the sense amp then actively converts the value on the BIT line to a “true” logic 0 or logic 1 voltage value. However, implementing a sense amp to correctly detect a logic 1 and logic 0 in such a prior art design is generally a complex and time consuming task. Accordingly, the time required for implementing a sense amp to detect the correct value of the BIT line in prior art implementations effectively increases the cost associated with such prior art implementations. Additionally, the sense amp circuitry itself adds to the cost of the prior art implementation and also consumes valuable surface space within such prior art designs.
In the prior art, SRAM memory is commonly implemented in banks (or “partitions”), with each bank comprising multiple groups of SRAM memory cells. For example, a memory bank of the prior art may comprise four groups of SRAM memory with each group comprising 256 SRAM memory cells
100
. Therefore, circuitry is commonly implemented in prior art designs to select a particular group of memory within a memory bank to access (e.g., in order to perform a read or write to a memory cell within the selected group). That is, circuitry is typically implemented in prior art designs to enable and disable a group of SRAM memory for read/write operations. For example, suppose an instruction desires to write data to a particular memory cell located within a first group of a memory bank that comprises four groups of memory cells. Circuitry is typically implemented to enable the first group of SRAM memory cells for read/write operations and disable the remaining three groups of SRAM memory cells.
Turning to
FIG. 2A
, a typical implementation for enabling/disabling a SRAM memory group is illustrated. As shown, circuitry is coupled to the BIT line of the SRAM structure
100
. Even though only SRAM cell
100
is shown, it should be understood that many such SRAM cells may be connected to the BIT line to form a group of SRAM cells. A precharger P-channel FET (PFET)
20
is coupled to the BIT line to precharge the BIT line to a high voltage level. The BIT line is received by an inverter
26
, which comprises PFET
10
and NFET
12
. The output of inverter
26
is fed back to a PFET holder
22
, which works to hold the BIT line to a high voltage level. When a read or write operation is desired for a particular group of SRAM cells, the precharger PFET
20
for that group of SRAM cells is turned off, thereby allowing the BIT line to be utilized for writing/reading data to/from SRAM cells within such group. That is, the precharger PFET
20
is turned off to enable a group of SRAM cells for read/write operations. Otherwise, for the groups of SRAM cells for which a read/write operation is not being performed, the precharger PFETs
20
for such groups remain turned on, thereby disabling such other groups of SRAM cells for read/write operations.
To further illustrate the operation of this prior art design, suppose that a processo

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