Large scale circuit device containing simultaneously accessible

Latch-up prevention for memory cells

Latch-up prevention for memory cells

Load-less four-transistor memory cell with different gate...

Loadless 4T SRAM cell with PMOS drivers

Loadless NMOS four transistor dynamic dual Vt SRAM cell

Loadless NMOS four transistor SRAM cell

Loadless SRAM

Local interconnect structure and process for six-transistor SRAM

Logic cell protected against random events

Logic circuit with a test capability

Logical operation circuit and logical operation method

Low AC power SRAM architecture

Low leakage current SRAM array

Low leakage current static random access memory

Low leakage high performance static random access memory...

Low power register memory element circuits

Low power SRAM

Low power SRAM memory cell having a single bit line

Low power SRAM memory cell having a single bit line