Techniques for reducing power consumption in memory cells

Details Techniques for reducing power consumption in memory cells Techniques for reducing power consumption in memory cells

2005-12-06

2005-12-06

Phung, Anh (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000

Reexamination Certificate

active

06972987

ABSTRACT:
Techniques are provided for reducing power consumption in memory cells. A static (SRAM) memory cell includes two cross coupled inverters. One or more transistors are coupled between the inverters and the power supply voltages. The transistors are turned OFF for a period of time during a memory state transition to block current flow between the high power supply voltage and the low power supply voltage to reduce power consumption.

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