Systems and devices for implementing sub-threshold memory...

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Reexamination Certificate

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C365S156000, C365S188000, C365S189050, C365S190000, C365S202000, C365S181000, C365S230050

Reexamination Certificate

active

07626850

ABSTRACT:
Various systems and methods for implementing memory devices are disclosed. For example, some embodiments of the present invention provide sub-threshold memory devices that include a differential bit cell. Such a differential bit cell includes two PMOS transistors, two NMOS transistors, and two inverters. The source of the first PMOS transistor and the source of the second PMOS transistor are electrically coupled to a bit line input, and the source of the first NMOS transistor and the source of the second NMOS transistor are electrically coupled to the bit line input. The gate of the first NMOS transistor and the gate of the second NMOS transistor are electrically coupled to a word line input. The gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically coupled to an inverted version of the word line input. The drain of the first PMOS transistor is electrically coupled to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is electrically coupled to the drain of the second NMOS transistor. In addition, the drain of the first PMOS transistor is electrically coupled to the drain of the second PMOS transistor by the first inverter, and the drain of the second PMOS transistor is electrically coupled to the drain of the first PMOS transistor by the second inverter.

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U.S. Appl. No. 11/736,419, filed Apr. 17, 2007, Charles M. Branch.
Commissioner, International Searching Authority, Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration, date of mailing Sep. 29, 2008, International Application No. PCT/US2008/060581, International Filing Date Apr. 17, 2008.

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