Structure of static random access memory with stress...

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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C365S154000, C365S051000, C365S072000, C257S418000, C257S903000

Reexamination Certificate

active

07471548

ABSTRACT:
An integrated circuit (IC) is provided that includes at least one static random access memory (SRAM) cell wherein performance of the SRAM cell is enhanced, yet with good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater. The gamma ratio is increased with degraded pFET device performance. Morever, in the inventive IC there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides an integrated circuit (IC) that comprises at least one SRAM cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the nFET and the pFET.

REFERENCES:
patent: 6573172 (2003-06-01), En et al.
patent: 6984564 (2006-01-01), Huang et al.
patent: 7232730 (2007-06-01), Chen et al.
patent: 7388267 (2008-06-01), Chen et al.
patent: 2003/0040158 (2003-02-01), Saitoh
patent: 2006/0099765 (2006-05-01), Yang
patent: 2008/0142895 (2008-06-01), Baiocco et al.

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