Hardened memory cell

Hidden refresh pseudo SRAM and hidden refresh method

Hierarchical six-transistor SRAM

High density planar SRAM cell with merged transistors

High density SRAM circuit with ratio independent memory cells

High density SRAM circuit with single-ended memory cells

High density two port memory cell

High density, high performance register file having improved clo

High density, high performance, single event upset immune data s

High impendance-coupled CMOS SRAM for improved single event immu

High performance metal gate polygate 8 transistor SRAM cell...

High performance single event upset hardened SRAM cell

High performance single event upset hardened SRAM cell

High performance static latches with complete single event upset

High reliability logic circuit for radiation environment

High speed CMOS latch with alternate data storage and test funct

High speed current mirror memory cell architecture

High speed memory cell with multiple port capability

High speed semiconductor memory apparatus including circuitry to

High speed zero power reset circuit for CMOS memory cells