High speed current mirror memory cell architecture

Details High speed current mirror memory cell architecture High speed current mirror memory cell architecture

1994-09-27

1996-02-06

Zarabian, A.

Static information storage and retrieval

Systems using particular element

Flip-flop

365190, G11C 1100

Patent

active

054901057

ABSTRACT:
A memory cell (i.e. CMMC) for use in GaAs circuits such as MESFETs wherein read and write operations can both be performed using as few as two access transistors biased as current mirrors to driver transistors of the cell. This new memory cell offers larger read access currents for faster access times and also faster write times than in a conventional memory cell. This cell does not require that the driver transistors be scaled with respect to the access transistors, resulting in a smaller cell area. In the CMMC, the gate of each access transistor is biased by a storage node voltage. The source node of each access transistor is biased by a word line which is pulled low, towards ground. As a result, each access transistor has a gate-source voltage of

REFERENCES:
patent: 4725981 (1988-02-01), Rutledge

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