High density, high performance, single event upset immune data s

Details High density, high performance, single event upset immune data s High density, high performance, single event upset immune data s

1987-03-09

1989-01-10

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Flip-flop

365156, 365181, 365205, G11C 700, G11C 702

Patent

active

047978040

ABSTRACT:
The data cell invention disclosed herein is a CMOS latch having a first CMOS inverter and a second CMOS inverter which have their respective storage nodes interconnected by cross-coupling connections which each include a gated polysilicon resistor. The respective storage nodes of the cell are connected through word line transfer gates to bit lines which serve to both write in and read out the state of the cell. The control gate of the word line transistors is also connected to the control gates of the respective gated polysilicon resistors in the cross-coupled connections for the cell. In normal operation, when the word line transfer gates are not conductive, the gated polysilicon resistors are also not conductive. When it is desired to write information into the cell during normal conditions, when the word line transfer gates are made conductive, the gated polysilicon resistors are also made conductive, thereby offering a minimum resistance to charge which is to be transferred between the respective storage nodes of the cell. However, during a single event upset condition, when one or more of the sensitive regions of the cell undergo an abrupt charge transfer due to the presence of cosmic rays or other ionizing radiation phenomena, since the gated polysilicon resistors are in their high resistance state, they impede the flow of any charges between the respective storage nodes of the cell. In this manner, after the single event upset has dissipated, the cell will have retained its original stored binary state. Thus, an enhanced resistance to single event upset conditions is provided by the invention while not imposing significant reductions in the speed of operation during normal conditions.

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