Hidden refresh pseudo SRAM and hidden refresh method

Details Hidden refresh pseudo SRAM and hidden refresh method Hidden refresh pseudo SRAM and hidden refresh method

2000-01-05

2001-09-04

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S222000

Reexamination Certificate

active

06285578

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer memory, and in particular, to a hidden refresh 2P2N pseudo SRAM (static random access memory) and its hidden refresh method.
2. Description of the Related Art
Memory plays an indispensable role in computer industries. Usually, a memory is classified into a DRAM (dynamic random access memory) and a SRAM (static random access memory) according it's respective data storage capability. DRAM is advantageous for its small size, but requires periodic refresh to prevent data loss due to current leakage. SRAM is advantageous for its simple operations, but occupies a large chip area.
FIG. 1A
(Prior Art) is a circuit diagram showing a conventional 1T1C memory cell of a DRAM. As shown in
FIG. 1A
, the 1T1C memory cell, known in the art, includes an access transistor T
1
and a storage capacitor CS. The access transistor T
1
has a source connected to the storage capacitor CS, a gate connected to a word line WL, and a drain connected to a bit line BL.
FIG. 1B
(Prior Art) is a diagram showing the 1T1C memory cell in
FIG. 1A
formed on a semiconductor substrate. As shown in
FIG. 1B
, a parasitic diode D
1
(PN junction) is formed between the source of the access transistor T
1
and the storage capacitor CS. Therefore, a logic “1” signal stored at the storage capacitor CS gradually decays even when the access transistor T
1
is shut off, where the word line WL is “0”. To prevent data loss, periodic refresh is performed for the DRAM, which reads the logic “1” signal stored at the storage capacitor CS, amplifies the logic “1” signal by a sense amplifier (not shown) connected to the bit line BL, and writes back the amplified signal.
FIG. 2
(Prior Art) is a circuit diagram showing a conventional 3T memory cell of a DRAM As shown in
FIG. 2
, the 3T memory cell, known in the art, includes a read transistor T
2
, a storage transistor T
3
, and a write transistor T
4
. The read transistor T
2
has a gate connected to a read word line RWL, a drain connected to a read bit line RBL, and a source. The storage capacitor T
3
has a gate, a drain connected to the source of the source of the read transistor T
2
, and a source connected to a negative source voltage of the DRAM. The write transistor T
4
has a gate connected to a write word line WWL, a drain connected to the word bit line WBL, and a source connected to the gate of the storage transistor T
3
. As in the 1T1C memory cell in
FIGS. 1A and 1B
, a logic “1” signal stored at the storage transistor T
3
decays due to a leakage current. To prevent data loss, periodic refresh is performed for the DRAM, which reads the logic “1” signal stored at the storage transistor T
3
through the read word line RWL, amplifies the logic “1” signal by a sense amplifier (not shown) connected to the bit line BL, and writes back the amplified signal through the write word line WWL.
FIG. 3
(Prior Art) is a circuit diagram showing a conventional 4T memory cell of a DRAM. As shown in
FIG. 3
, the 4T memory cell, known in the art, includes four NMOS transistors N
1
, N
2
, N
3
and N
4
. The NMOS transistors N
1
and N
2
have their sources connected to a negative source voltage, and gates and sources cross coupled to each other to form a cross-couple latch storing a pair of signals S/S′. The NMOS transistors N
3
and N
4
have their gates connected to the word line WL, and drains and sources connected to a pair of bit lines BL/BL′ and the drains of the NMOS transistors N
1
and N
2
, respectively, to access the pair of signals S/S′ stored at the cross-couple latch. The storage data swing of the pair of signals S/S′ is a positive source voltage of the DRAM minus a threshold voltage (VDD−VTN) of the NMOS transistors N
1
, N
2
, N
3
and N
4
. When the NMOS transistors N
3
and N
4
are closed (i.e., the word line WL is “0”) and the pair of signals S/S′ at the cross-couple latch are “0”/“1”(VDD−VTN), the signal S is not floating, whereas the signal S′ is floating. Therefore, as in the 1T1C memory cell in
FIGS. 1A and 1B
, periodic refresh is performed to prevent data loss at the signal S′, which only opens the word line WL for a short time to ensure that load L connected to the pair of bit lines BL/BL′ provides sufficient refresh currents. The load L can be controlled to function only when performing pre-charging and refresh operations of the DRAM, thereby reducing the power consumed.
Compared with the 1T1C memory cell which is manufactured using a stack process or a trench process, the 4T memory cell is manufactured using a standard CMOS process, known in the art. Further, the 4T memory cell stores data differentially (such as the pair of signals S/S′) and has a larger noise margin and a higher access speed. Therefore, most pseudo RAMs are structured with 4T memory cells to be manufactured using a standard CMOS process.
FIGS. 4A and 4B
(Prior Art) are circuit diagrams showing a 6T memory cell of a SRAM, known in the art. To prevent floating of the differential signals S/S′ in the 4T memory cell of
FIG. 3
, two PMOS transistors P
1
and P
2
are included in the 4T memory cell to obtain a SRAM cell which operates as the 4T memory cell, as shown in FIG.
4
A. The PMOS transistors P
1
and P
2
have their sources connected to a positive source voltage of the SRAM, gates connected to the drains of the NMOS transistors N
2
and N
1
, and drains connected to the drains of the NMOS transistors N
1
and N
2
, respectively. Further, the access NMOS transistors N
3
and N
4
in
FIG. 4A
can also be replaced with two PMOS transistors P
3
and P
4
, as shown in FIG.
4
B. In this case, the PMOS transistors P
1
and P
2
constitute a cross-couple latch, and the NMOS transistors N
1
and N
2
are provided only to prevent floating of the differential signals S/S′.
Further, since the leakage current is mostly derived from reverse bias leakage of the parasitic diode, the PMOS transistors P
1
and P
2
can be also replaced with two resistors R
1
and R
2
(10
10
~10
11&OHgr;
), as shown in
FIG. 4C
(Prior Art), that provide a supply current which is larger than the leakage current and prevent data loss of the differential signals S/S′. In this case, the resistors R
1
and R
2
can be formed above the NMOS transistors and occupy the same chip area as the 4T memory cell. Further, the resistors R
1
and R
2
in
FIG. 4C
can be replaced with two thin film transistors TFT
1
and TFT
2
to obtain a larger noise margin and a lower standby current, as shown in
FIG. 4D
(Prior Art). In this case, the thin film transistors TFT
1
and TFT
2
can also be formed above the NMOS transistors and occupy the same chip area as the 4T memory cell.
From the above, a pseudo SRAM with 4T memory cells can be manufactured using a standard CMOS process, reducing chip area by two PMOS transistors, and operate as a standard SRAM. However, it is also necessary to include a refresh operation (that is, opening all word lines for a short time) except normal read/write operations, which result in power loss.
FIG. 5A
(Prior Art) is a circuit diagram showing a driver of a conventional pseudo SRAM. As shown in
FIG. 5A
, the driver of the memory array
10
includes a row address decoder
11
, a column address decoder
12
, a multiplexor
13
, a refresh counter
14
, and a controller
15
. The multiplexor
13
, under the control of the controller
15
, selectively transfers a row address RA or a counting result of the refresh counter
14
to the row address decoder
11
to generate a driving signal of a corresponding word line of the memory array
10
. The column address decoder
12
receives a column address CA to generate a driving signal of a corresponding bit line of the memory array
10
. Therefore, access and refresh operations of the memory array
10
can be performed according to the driving signals generated by the row address decoder
11
and the column address decoder
12
.
The refresh counter
14
in
FIG. 5A
can be

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