High speed zero power reset circuit for CMOS memory cells

Details High speed zero power reset circuit for CMOS memory cells High speed zero power reset circuit for CMOS memory cells

1986-12-19

1989-08-15

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Flip-flop

365218, 365226, 365190, G11C 700, G11C 1140

Patent

active

048581828

ABSTRACT:
A reset circuit for a CMOS memory array is disclosed wherein the voltage supply for the standard six transistor memory cell is replaced by a pair of parallel connected transistors disposed between a fixed voltage source and the memory cell. The transistors are controlled by the reset signal and are complementary in that one is n-channel and the other is p-channel. The n-channel transistor is sized to prevent excess current flow to the memory cells to prevent an excessive charge build up therein for a logical "1" representation. In addition, the n-channel transistor provides a Vtn drop thereacross to prevent current flow in the memory cells during reset.

REFERENCES:
patent: 3757313 (1973-09-01), Hines et al.
patent: 4418401 (1983-11-01), Bansal
patent: 4489404 (1984-12-01), Yasuoka
patent: 4567578 (1986-01-01), Cohen et al.

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