High performance single event upset hardened SRAM cell

Details High performance single event upset hardened SRAM cell High performance single event upset hardened SRAM cell

2008-07-08

2008-07-08

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S149000, C365S189050, C365S200000, C365S201000, C365S230080, C711S104000, C714S048000

Reexamination Certificate

active

07397692

ABSTRACT:
An SRAM cell. The SRAM cell includes a first CMOS inverter and a second CMOS inverter, an input of the first inverter connected to an output of the second inverter and an input of the second inverter connected to an output of the first inverter, a first MOSFET interposed between an output of the first CMOS inverter and a first plate of a first capacitor, a second plate of the first capacitor connected to a high voltage terminal of a power supply; a second MOSFET interposed between an output of the second CMOS inverter and a first plate of a second capacitor, a second plate of the second capacitor connected to the high voltage terminal of the power supply; and a control signal line connected to a gate of the first MOSFET and a gate of the second MOSFET.

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