High speed CMOS latch with alternate data storage and test funct

Details High speed CMOS latch with alternate data storage and test funct High speed CMOS latch with alternate data storage and test funct

1986-09-30

1988-08-30

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Flip-flop

365154, 365201, 365189, 377 79, 371 13, G11C 1100, G11C 700, G11C 2900, G11C 1900

Patent

active

047681675

ABSTRACT:
A CMOS flip-flop circuit is disclosed which enables a single side pull-down operation for inputting test signals during a test mode and alternately a dual side push-pull operation for inputting data signals during the normal use of the circuit. A pair of inverter circuits selectively feed complementary data signals to opposite sides of a bistable circuit so that the circuit operates in the push-pull manner thereby decreasing the switching time of the flip-flop. A pair of transmission gates, which are coupled to outputs of the inverter circuits, electrically isolate any noise appearing at a data input from the bistable circuit. During a test mode of the flip-flop, a test signal is fed into one side of the bistable circuit and facilitates a single side pull-down operation of the flip-flop. Two such flip-flop circuits are concatenated in a push-pull cascaded connection to provide a shift register latch.

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IBM Techn. Discl. Bull., vol. 13, No. 2, Jul. 1970, pp. 493-494, "Complementary Shift Register" by Hastings.
IBM Technical Disclosure Bulletin, vol. 12, No. 12, May 1970, pp. 2138-2139, "Static Field Effect Trans. Shift Register" by Gaensslen et al.
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