High performance static latches with complete single event upset

Details High performance static latches with complete single event upset High performance static latches with complete single event upset

1991-11-15

1994-04-26

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Flip-flop

365154, 365200, 371 103, G11C 1100, G11C 2900

Patent

active

053071425

ABSTRACT:
An asymmetric response latch providing immunity to single event upset without loss of speed. The latch has cross-coupled inverters having a hardened logic state and a soft state, wherein the logic state of the first inverter can only be changed when the voltage on the coupling node of that inverter is low and the logic state of the second inverter can only be changed when the coupling of that inverter is high. One of more of the asymmetric response latches may be configured into a memory cell having complete immunity, which protects information rather than logic states.

REFERENCES:
patent: 4053873 (1977-10-01), Freeman et al.
patent: 4460998 (1984-07-01), Yamada et al.
patent: 4744056 (1988-05-01), Yu et al.
patent: 4748594 (1988-05-01), Iida
patent: 4797804 (1989-01-01), Rockett, Jr.
patent: 4805148 (1989-02-01), Diehl-Nagle et al.
patent: 4809226 (1989-02-01), Ochoa, Jr.
patent: 4852060 (1989-07-01), Rockett, Jr.
patent: 4912675 (1990-03-01), Blake et al.
patent: 4914629 (1990-04-01), Blake et al.
patent: 4956814 (1990-09-01), Houston
patent: 4956815 (1990-09-01), Houston
patent: 4969125 (1990-11-01), Ciraula et al.
patent: 5046044 (1991-09-01), Houston et al.
patent: 5051949 (1991-09-01), Young
patent: 5053848 (1991-10-01), Houston et al.
patent: 5134581 (1992-07-01), Ishibashi et al.
T. M. Mnich et al., "Comparison of Analytical Models and Experimental Results for Single Event Upset in CMOS SRAMs," IEEE Transactions on Nuclear Science, vol. NS-30, No. 6, Dec. 1983 pp. 4620-4623.
A. Ochoa, Jr. et al., "A Proposed New Structure for SEU Immunity in SRAM Employing Drain Resistance," IEEE Electron Device Letters vol. EDL-8, No. 11, Nov. 1987, pp. 537-539.
L. Rockett, Jr., "An SEU-Hardened CMOS Data Latch Design," IEEE Transactions on Nuclear Science, vol. 35, No. 6, Dec., 1988 pp. 1682-1687.
L. Rockett, Jr., "Designing Hardened Bulk/Epi CMOS Circuits," Proceedings of the IEEE, vol. 76, No. 11, Nov., 1988, pp. 1474-1483.
J. Pridmore, "Designing Hardened CMOS/SOS Circuits," Proceedings of the IEEE, vol. 76, No. 11, Nov. 1988, pp. 1483-1490.
H. Weaver et al., "An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM," IEEE Transactions on Nuclear Science, vol. NS-34, 1987, p. 1281.

Affiliated with

Also associated with

Rating

High performance static latches with complete single event upset does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High performance static latches with complete single event upset, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High performance static latches with complete single event upset will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1715244